output reg [7:0] data
 always @ (*) begin
 case
 1:data= 8'b00000011; //number 0
 2:data= 8'b00100101; //number 2
 3:data= 8'b10011001; //number 4
 default:data=8'b00000011;
 endcase
 end

input clock,
input reset,
output [7:0] out
reg [31:0] counter;
always @ (posedge clock) begin
if(reset==1)  counter <= 0;
else counter <= counter + 1;
end

always @ (posedge clock) begin
if(reset==1)  case <= 1;
else case <= case + 1;
if(case==3) reset<=1;
end

always @ (*) begin
 case(counter)
  1: data= 8'b00000011; //number 0
  2: data= 8'b00100101; //number 2
  3: data= 8'b10011001; //number 4
  default:data=8'b00000011;
 endcase
 end

always @ (posedge clock) begin
  if(reset==1 || counter == 3)  counter <= 1;
  else counter <= counter + 1;
end