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  1. /*
  2.  * ar8216.c: AR8216 switch driver
  3.  *
  4.  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  5.  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  6.  *
  7.  * This program is free software; you can redistribute it and/or
  8.  * modify it under the terms of the GNU General Public License
  9.  * as published by the Free Software Foundation; either version 2
  10.  * of the License, or (at your option) any later version.
  11.  *
  12.  * This program is distributed in the hope that it will be useful,
  13.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15.  * GNU General Public License for more details.
  16.  */
  17.  
  18. #include <linux/if.h>
  19. #include <linux/module.h>
  20. #include <linux/init.h>
  21. #include <linux/list.h>
  22. #include <linux/if_ether.h>
  23. #include <linux/skbuff.h>
  24. #include <linux/netdevice.h>
  25. #include <linux/netlink.h>
  26. #include <linux/bitops.h>
  27. #include <net/genetlink.h>
  28. #include <linux/switch.h>
  29. #include <linux/delay.h>
  30. #include <linux/phy.h>
  31. #include <linux/netdevice.h>
  32. #include <linux/etherdevice.h>
  33. #include <linux/lockdep.h>
  34. #include <linux/ar8216_platform.h>
  35. #include <linux/workqueue.h>
  36. #include <linux/of_device.h>
  37. #include <linux/leds.h>
  38. #include <linux/gpio.h>
  39.  
  40. #include "ar8216.h"
  41.  
  42. /* size of the vlan table */
  43. #define AR8X16_MAX_VLANS    128
  44. #define AR8X16_PROBE_RETRIES    10
  45. #define AR8X16_MAX_PORTS    8
  46.  
  47. #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  48.  
  49. struct ar8xxx_priv;
  50.  
  51. #define AR8XXX_CAP_GIGE         BIT(0)
  52. #define AR8XXX_CAP_MIB_COUNTERS     BIT(1)
  53.  
  54. enum {
  55.     AR8XXX_VER_AR8216 = 0x01,
  56.     AR8XXX_VER_AR8236 = 0x03,
  57.     AR8XXX_VER_AR8316 = 0x10,
  58.     AR8XXX_VER_AR8327 = 0x12,
  59.     AR8XXX_VER_AR8337 = 0x13,
  60. };
  61.  
  62. struct ar8xxx_mib_desc {
  63.     unsigned int size;
  64.     unsigned int offset;
  65.     const char *name;
  66. };
  67.  
  68. struct ar8xxx_chip {
  69.     unsigned long caps;
  70.  
  71.     int (*hw_init)(struct ar8xxx_priv *priv);
  72.     void (*cleanup)(struct ar8xxx_priv *priv);
  73.  
  74.     void (*init_globals)(struct ar8xxx_priv *priv);
  75.     void (*init_port)(struct ar8xxx_priv *priv, int port);
  76.     void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
  77.     u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
  78.     int (*atu_flush)(struct ar8xxx_priv *priv);
  79.     void (*vtu_flush)(struct ar8xxx_priv *priv);
  80.     void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vlan);
  81.  
  82.     const struct ar8xxx_mib_desc *mib_decs;
  83.     unsigned num_mibs;
  84. };
  85.  
  86. enum ar8327_led_pattern {
  87.     AR8327_LED_PATTERN_OFF = 0,
  88.     AR8327_LED_PATTERN_BLINK,
  89.     AR8327_LED_PATTERN_ON,
  90.     AR8327_LED_PATTERN_RULE,
  91. };
  92.  
  93. struct ar8327_led_entry {
  94.     unsigned reg;
  95.     unsigned shift;
  96. };
  97.  
  98. struct ar8327_led {
  99.     struct led_classdev cdev;
  100.     struct ar8xxx_priv *sw_priv;
  101.  
  102.     char *name;
  103.     bool active_low;
  104.     u8 led_num;
  105.     enum ar8327_led_mode mode;
  106.  
  107.     struct mutex mutex;
  108.     spinlock_t lock;
  109.     struct work_struct led_work;
  110.     bool enable_hw_mode;
  111.     enum ar8327_led_pattern pattern;
  112. };
  113.  
  114. struct ar8216_data {
  115.     u8 vlan_tagged;
  116. };
  117.  
  118. struct ar8327_data {
  119.     u8 vlan_tagged[AR8X16_MAX_VLANS];
  120.     u32 port0_status;
  121.     u32 port6_status;
  122.  
  123.     struct ar8327_led **leds;
  124.     unsigned int num_leds;
  125. };
  126.  
  127. struct ar8xxx_priv {
  128.     struct switch_dev dev;
  129.     struct mii_bus *mii_bus;
  130.     struct phy_device *phy;
  131.  
  132.     u32 (*read)(struct ar8xxx_priv *priv, int reg);
  133.     void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
  134.     u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
  135.  
  136.     int (*get_port_link)(unsigned port);
  137.  
  138.     const struct net_device_ops *ndo_old;
  139.     struct net_device_ops ndo;
  140.     struct mutex reg_mutex;
  141.     u8 chip_ver;
  142.     u8 chip_rev;
  143.     const struct ar8xxx_chip *chip;
  144.     union {
  145.         struct ar8216_data ar8216;
  146.         struct ar8327_data ar8327;
  147.     } chip_data;
  148.     bool initialized;
  149.     bool port4_phy;
  150.     char buf[2048];
  151.  
  152.     bool init;
  153.     bool mii_lo_first;
  154.  
  155.     struct mutex mib_lock;
  156.     struct delayed_work mib_work;
  157.     int mib_next_port;
  158.     u64 *mib_stats;
  159.  
  160.     struct list_head list;
  161.     unsigned int use_count;
  162.  
  163.     /* all fields below are cleared on reset */
  164.     bool vlan;
  165.     u16 vlan_id[AR8X16_MAX_VLANS];
  166.     u8 vlan_table[AR8X16_MAX_VLANS];
  167.     u16 pvid[AR8X16_MAX_PORTS];
  168.  
  169.     /* mirroring */
  170.     bool mirror_rx;
  171.     bool mirror_tx;
  172.     int source_port;
  173.     int monitor_port;
  174. };
  175.  
  176. #define MIB_DESC(_s , _o, _n)   \
  177.     {           \
  178.         .size = (_s),   \
  179.         .offset = (_o), \
  180.         .name = (_n),   \
  181.     }
  182.  
  183. static const struct ar8xxx_mib_desc ar8216_mibs[] = {
  184.     MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
  185.     MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
  186.     MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
  187.     MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
  188.     MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
  189.     MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
  190.     MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
  191.     MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
  192.     MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
  193.     MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
  194.     MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
  195.     MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
  196.     MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
  197.     MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
  198.     MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
  199.     MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
  200.     MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
  201.     MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
  202.     MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
  203.     MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
  204.     MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
  205.     MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
  206.     MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
  207.     MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
  208.     MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
  209.     MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
  210.     MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
  211.     MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
  212.     MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
  213.     MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
  214.     MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
  215.     MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
  216.     MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
  217.     MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
  218.     MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
  219.     MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
  220.     MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
  221. };
  222.  
  223. static const struct ar8xxx_mib_desc ar8236_mibs[] = {
  224.     MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
  225.     MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
  226.     MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
  227.     MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
  228.     MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
  229.     MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
  230.     MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
  231.     MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
  232.     MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
  233.     MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
  234.     MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
  235.     MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
  236.     MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
  237.     MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
  238.     MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
  239.     MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
  240.     MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
  241.     MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
  242.     MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
  243.     MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
  244.     MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
  245.     MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
  246.     MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
  247.     MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
  248.     MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
  249.     MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
  250.     MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
  251.     MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
  252.     MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
  253.     MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
  254.     MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
  255.     MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
  256.     MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
  257.     MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
  258.     MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
  259.     MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
  260.     MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
  261.     MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
  262.     MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
  263. };
  264.  
  265. static DEFINE_MUTEX(ar8xxx_dev_list_lock);
  266. static LIST_HEAD(ar8xxx_dev_list);
  267.  
  268. static inline struct ar8xxx_priv *
  269. swdev_to_ar8xxx(struct switch_dev *swdev)
  270. {
  271.     return container_of(swdev, struct ar8xxx_priv, dev);
  272. }
  273.  
  274. static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
  275. {
  276.     return priv->chip->caps & AR8XXX_CAP_GIGE;
  277. }
  278.  
  279. static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
  280. {
  281.     return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
  282. }
  283.  
  284. static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
  285. {
  286.     return priv->chip_ver == AR8XXX_VER_AR8216;
  287. }
  288.  
  289. static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
  290. {
  291.     return priv->chip_ver == AR8XXX_VER_AR8236;
  292. }
  293.  
  294. static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
  295. {
  296.     return priv->chip_ver == AR8XXX_VER_AR8316;
  297. }
  298.  
  299. static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
  300. {
  301.     return priv->chip_ver == AR8XXX_VER_AR8327;
  302. }
  303.  
  304. static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
  305. {
  306.     return priv->chip_ver == AR8XXX_VER_AR8337;
  307. }
  308.  
  309. static inline void
  310. split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
  311. {
  312.     regaddr >>= 1;
  313.     *r1 = regaddr & 0x1e;
  314.  
  315.     regaddr >>= 5;
  316.     *r2 = regaddr & 0x7;
  317.  
  318.     regaddr >>= 3;
  319.     *page = regaddr & 0x1ff;
  320. }
  321.  
  322. static u32
  323. ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
  324. {
  325.     struct mii_bus *bus = priv->mii_bus;
  326.     u16 r1, r2, page;
  327.     u16 lo, hi;
  328.  
  329.     split_addr((u32) reg, &r1, &r2, &page);
  330.  
  331.     mutex_lock(&bus->mdio_lock);
  332.  
  333.     bus->write(bus, 0x18, 0, page);
  334.     usleep_range(1000, 2000); /* wait for the page switch to propagate */
  335.     lo = bus->read(bus, 0x10 | r2, r1);
  336.     hi = bus->read(bus, 0x10 | r2, r1 + 1);
  337.  
  338.     mutex_unlock(&bus->mdio_lock);
  339.  
  340.     return (hi << 16) | lo;
  341. }
  342.  
  343. static void
  344. ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
  345. {
  346.     struct mii_bus *bus = priv->mii_bus;
  347.     u16 r1, r2, r3;
  348.     u16 lo, hi;
  349.  
  350.     split_addr((u32) reg, &r1, &r2, &r3);
  351.     lo = val & 0xffff;
  352.     hi = (u16) (val >> 16);
  353.  
  354.     mutex_lock(&bus->mdio_lock);
  355.  
  356.     bus->write(bus, 0x18, 0, r3);
  357.     usleep_range(1000, 2000); /* wait for the page switch to propagate */
  358.     if (priv->mii_lo_first) {
  359.         bus->write(bus, 0x10 | r2, r1, lo);
  360.         bus->write(bus, 0x10 | r2, r1 + 1, hi);
  361.     } else {
  362.         bus->write(bus, 0x10 | r2, r1 + 1, hi);
  363.         bus->write(bus, 0x10 | r2, r1, lo);
  364.     }
  365.  
  366.     mutex_unlock(&bus->mdio_lock);
  367. }
  368.  
  369. static u32
  370. ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
  371. {
  372.     struct mii_bus *bus = priv->mii_bus;
  373.     u16 r1, r2, page;
  374.     u16 lo, hi;
  375.     u32 ret;
  376.  
  377.     split_addr((u32) reg, &r1, &r2, &page);
  378.  
  379.     mutex_lock(&bus->mdio_lock);
  380.  
  381.     bus->write(bus, 0x18, 0, page);
  382.     usleep_range(1000, 2000); /* wait for the page switch to propagate */
  383.  
  384.     lo = bus->read(bus, 0x10 | r2, r1);
  385.     hi = bus->read(bus, 0x10 | r2, r1 + 1);
  386.  
  387.     ret = hi << 16 | lo;
  388.     ret &= ~mask;
  389.     ret |= val;
  390.  
  391.     lo = ret & 0xffff;
  392.     hi = (u16) (ret >> 16);
  393.  
  394.     if (priv->mii_lo_first) {
  395.         bus->write(bus, 0x10 | r2, r1, lo);
  396.         bus->write(bus, 0x10 | r2, r1 + 1, hi);
  397.     } else {
  398.         bus->write(bus, 0x10 | r2, r1 + 1, hi);
  399.         bus->write(bus, 0x10 | r2, r1, lo);
  400.     }
  401.  
  402.     mutex_unlock(&bus->mdio_lock);
  403.  
  404.     return ret;
  405. }
  406.  
  407.  
  408. static void
  409. ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
  410.              u16 dbg_addr, u16 dbg_data)
  411. {
  412.     struct mii_bus *bus = priv->mii_bus;
  413.  
  414.     mutex_lock(&bus->mdio_lock);
  415.     bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
  416.     bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
  417.     mutex_unlock(&bus->mdio_lock);
  418. }
  419.  
  420. static void
  421. ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
  422. {
  423.     struct mii_bus *bus = priv->mii_bus;
  424.  
  425.     mutex_lock(&bus->mdio_lock);
  426.     bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
  427.     bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
  428.     mutex_unlock(&bus->mdio_lock);
  429. }
  430.  
  431. static inline u32
  432. ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
  433. {
  434.     return priv->rmw(priv, reg, mask, val);
  435. }
  436.  
  437. static inline void
  438. ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
  439. {
  440.     priv->rmw(priv, reg, 0, val);
  441. }
  442.  
  443. static int
  444. ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
  445.         unsigned timeout)
  446. {
  447.     int i;
  448.  
  449.     for (i = 0; i < timeout; i++) {
  450.         u32 t;
  451.  
  452.         t = priv->read(priv, reg);
  453.         if ((t & mask) == val)
  454.             return 0;
  455.  
  456.         usleep_range(1000, 2000);
  457.     }
  458.  
  459.     return -ETIMEDOUT;
  460. }
  461.  
  462. static int
  463. ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
  464. {
  465.     unsigned mib_func;
  466.     int ret;
  467.  
  468.     lockdep_assert_held(&priv->mib_lock);
  469.  
  470.     if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
  471.         mib_func = AR8327_REG_MIB_FUNC;
  472.     else
  473.         mib_func = AR8216_REG_MIB_FUNC;
  474.  
  475.     /* Capture the hardware statistics for all ports */
  476.     ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
  477.  
  478.     /* Wait for the capturing to complete. */
  479.     ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
  480.     if (ret)
  481.         goto out;
  482.  
  483.     ret = 0;
  484.  
  485. out:
  486.     return ret;
  487. }
  488.  
  489. static int
  490. ar8xxx_mib_capture(struct ar8xxx_priv *priv)
  491. {
  492.     return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
  493. }
  494.  
  495. static int
  496. ar8xxx_mib_flush(struct ar8xxx_priv *priv)
  497. {
  498.     return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
  499. }
  500.  
  501. static void
  502. ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
  503. {
  504.     unsigned int base;
  505.     u64 *mib_stats;
  506.     int i;
  507.  
  508.     WARN_ON(port >= priv->dev.ports);
  509.  
  510.     lockdep_assert_held(&priv->mib_lock);
  511.  
  512.     if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
  513.         base = AR8327_REG_PORT_STATS_BASE(port);
  514.     else if (chip_is_ar8236(priv) ||
  515.          chip_is_ar8316(priv))
  516.         base = AR8236_REG_PORT_STATS_BASE(port);
  517.     else
  518.         base = AR8216_REG_PORT_STATS_BASE(port);
  519.  
  520.     mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
  521.     for (i = 0; i < priv->chip->num_mibs; i++) {
  522.         const struct ar8xxx_mib_desc *mib;
  523.         u64 t;
  524.  
  525.         mib = &priv->chip->mib_decs[i];
  526.         t = priv->read(priv, base + mib->offset);
  527.         if (mib->size == 2) {
  528.             u64 hi;
  529.  
  530.             hi = priv->read(priv, base + mib->offset + 4);
  531.             t |= hi << 32;
  532.         }
  533.  
  534.         if (flush)
  535.             mib_stats[i] = 0;
  536.         else
  537.             mib_stats[i] += t;
  538.     }
  539. }
  540.  
  541. static void
  542. ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
  543.               struct switch_port_link *link)
  544. {
  545.     u32 status;
  546.     u32 speed;
  547.  
  548.     memset(link, '\0', sizeof(*link));
  549.  
  550.     status = priv->chip->read_port_status(priv, port);
  551.  
  552.     link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
  553.     if (link->aneg) {
  554.         link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
  555.     } else {
  556.         link->link = true;
  557.  
  558.         if (priv->get_port_link) {
  559.             int err;
  560.  
  561.             err = priv->get_port_link(port);
  562.             if (err >= 0)
  563.                 link->link = !!err;
  564.         }
  565.     }
  566.  
  567.     if (!link->link)
  568.         return;
  569.  
  570.     link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
  571.     link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
  572.     link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
  573.  
  574.     speed = (status & AR8216_PORT_STATUS_SPEED) >>
  575.          AR8216_PORT_STATUS_SPEED_S;
  576.  
  577.     switch (speed) {
  578.     case AR8216_PORT_SPEED_10M:
  579.         link->speed = SWITCH_PORT_SPEED_10;
  580.         break;
  581.     case AR8216_PORT_SPEED_100M:
  582.         link->speed = SWITCH_PORT_SPEED_100;
  583.         break;
  584.     case AR8216_PORT_SPEED_1000M:
  585.         link->speed = SWITCH_PORT_SPEED_1000;
  586.         break;
  587.     default:
  588.         link->speed = SWITCH_PORT_SPEED_UNKNOWN;
  589.         break;
  590.     }
  591. }
  592.  
  593. static struct sk_buff *
  594. ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
  595. {
  596.     struct ar8xxx_priv *priv = dev->phy_ptr;
  597.     unsigned char *buf;
  598.  
  599.     if (unlikely(!priv))
  600.         goto error;
  601.  
  602.     if (!priv->vlan)
  603.         goto send;
  604.  
  605.     if (unlikely(skb_headroom(skb) < 2)) {
  606.         if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
  607.             goto error;
  608.     }
  609.  
  610.     buf = skb_push(skb, 2);
  611.     buf[0] = 0x10;
  612.     buf[1] = 0x80;
  613.  
  614. send:
  615.     return skb;
  616.  
  617. error:
  618.     dev_kfree_skb_any(skb);
  619.     return NULL;
  620. }
  621.  
  622. static void
  623. ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
  624. {
  625.     struct ar8xxx_priv *priv;
  626.     unsigned char *buf;
  627.     int port, vlan;
  628.  
  629.     priv = dev->phy_ptr;
  630.     if (!priv)
  631.         return;
  632.  
  633.     /* don't strip the header if vlan mode is disabled */
  634.     if (!priv->vlan)
  635.         return;
  636.  
  637.     /* strip header, get vlan id */
  638.     buf = skb->data;
  639.     skb_pull(skb, 2);
  640.  
  641.     /* check for vlan header presence */
  642.     if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
  643.         return;
  644.  
  645.     port = buf[0] & 0xf;
  646.  
  647.     /* no need to fix up packets coming from a tagged source */
  648.     if (priv->chip_data.ar8216.vlan_tagged & BIT(port))
  649.         return;
  650.  
  651.     /* lookup port vid from local table, the switch passes an invalid vlan id */
  652.     vlan = priv->vlan_id[priv->pvid[port]];
  653.  
  654.     buf[14 + 2] &= 0xf0;
  655.     buf[14 + 2] |= vlan >> 8;
  656.     buf[15 + 2] = vlan & 0xff;
  657. }
  658.  
  659. static int
  660. ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
  661. {
  662.     int timeout = 20;
  663.     u32 t = 0;
  664.  
  665.     while (1) {
  666.         t = priv->read(priv, reg);
  667.         if ((t & mask) == val)
  668.             return 0;
  669.  
  670.         if (timeout-- <= 0)
  671.             break;
  672.  
  673.         udelay(10);
  674.     }
  675.  
  676.     pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
  677.            (unsigned int) reg, t, mask, val);
  678.     return -ETIMEDOUT;
  679. }
  680.  
  681. static void
  682. ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
  683. {
  684.     if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
  685.         return;
  686.     if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
  687.         val &= AR8216_VTUDATA_MEMBER;
  688.         val |= AR8216_VTUDATA_VALID;
  689.         priv->write(priv, AR8216_REG_VTU_DATA, val);
  690.     }
  691.     op |= AR8216_VTU_ACTIVE;
  692.     priv->write(priv, AR8216_REG_VTU, op);
  693. }
  694.  
  695. static void
  696. ar8216_vtu_flush(struct ar8xxx_priv *priv)
  697. {
  698.     ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
  699. }
  700.  
  701. static void
  702. ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vlan)
  703. {
  704.     u32 op;
  705.  
  706.     u32 vid = priv->vlan_id[vlan];
  707.     u32 port_mask = priv->vlan_table[vlan];
  708.    
  709.     op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
  710.    
  711.     ar8216_vtu_op(priv, op, port_mask);
  712. }
  713.  
  714. static int
  715. ar8216_atu_flush(struct ar8xxx_priv *priv)
  716. {
  717.     int ret;
  718.  
  719.     ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
  720.     if (!ret)
  721.         priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
  722.  
  723.     return ret;
  724. }
  725.  
  726. static u32
  727. ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
  728. {
  729.     return priv->read(priv, AR8216_REG_PORT_STATUS(port));
  730. }
  731.  
  732. static void
  733. ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
  734. {
  735.     u32 header;
  736.     u32 egress, ingress;
  737.     u32 pvid;
  738.  
  739.     if (priv->vlan) {
  740.         pvid = priv->vlan_id[priv->pvid[port]];
  741.         if (priv->chip_data.ar8216.vlan_tagged & BIT(port))
  742.             egress = AR8216_OUT_ADD_VLAN;
  743.         else
  744.             egress = AR8216_OUT_STRIP_VLAN;
  745.         ingress = AR8216_IN_SECURE;
  746.     } else {
  747.         pvid = port;
  748.         egress = AR8216_OUT_KEEP;
  749.         ingress = AR8216_IN_PORT_ONLY;
  750.     }
  751.    
  752.    
  753.  
  754.     if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
  755.         header = AR8216_PORT_CTRL_HEADER;
  756.     else
  757.         header = 0;
  758.  
  759.     ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
  760.            AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
  761.            AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
  762.            AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
  763.            AR8216_PORT_CTRL_LEARN | header |
  764.            (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
  765.            (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
  766.  
  767.     ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
  768.            AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
  769.            AR8216_PORT_VLAN_DEFAULT_ID,
  770.            (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
  771.            (ingress << AR8216_PORT_VLAN_MODE_S) |
  772.            (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
  773. }
  774.  
  775. static int
  776. ar8216_hw_init(struct ar8xxx_priv *priv)
  777. {
  778.     return 0;
  779. }
  780.  
  781. static void
  782. ar8216_init_globals(struct ar8xxx_priv *priv)
  783. {
  784.     /* standard atheros magic */
  785.     priv->write(priv, 0x38, 0xc000050e);
  786.  
  787.     ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
  788.            AR8216_GCTRL_MTU, 1518 + 8 + 2);
  789. }
  790.  
  791. static void
  792. ar8216_init_port(struct ar8xxx_priv *priv, int port)
  793. {
  794.     /* Enable port learning and tx */
  795.     priv->write(priv, AR8216_REG_PORT_CTRL(port),
  796.         AR8216_PORT_CTRL_LEARN |
  797.         (4 << AR8216_PORT_CTRL_STATE_S));
  798.  
  799.     priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
  800.  
  801.     if (port == AR8216_PORT_CPU) {
  802.         priv->write(priv, AR8216_REG_PORT_STATUS(port),
  803.             AR8216_PORT_STATUS_LINK_UP |
  804.             (ar8xxx_has_gige(priv) ?
  805.                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
  806.             AR8216_PORT_STATUS_TXMAC |
  807.             AR8216_PORT_STATUS_RXMAC |
  808.             (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
  809.             (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
  810.             AR8216_PORT_STATUS_DUPLEX);
  811.     } else {
  812.         priv->write(priv, AR8216_REG_PORT_STATUS(port),
  813.             AR8216_PORT_STATUS_LINK_AUTO);
  814.     }
  815. }
  816.  
  817. static const struct ar8xxx_chip ar8216_chip = {
  818.     .caps = AR8XXX_CAP_MIB_COUNTERS,
  819.  
  820.     .hw_init = ar8216_hw_init,
  821.     .init_globals = ar8216_init_globals,
  822.     .init_port = ar8216_init_port,
  823.     .setup_port = ar8216_setup_port,
  824.     .read_port_status = ar8216_read_port_status,
  825.     .atu_flush = ar8216_atu_flush,
  826.     .vtu_flush = ar8216_vtu_flush,
  827.     .vtu_load_vlan = ar8216_vtu_load_vlan,
  828.  
  829.     .num_mibs = ARRAY_SIZE(ar8216_mibs),
  830.     .mib_decs = ar8216_mibs,
  831. };
  832.  
  833. static void
  834. ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
  835. {
  836.     u32 egress, ingress;
  837.     u32 pvid;
  838.  
  839.     if (priv->vlan) {
  840.         pvid = priv->vlan_id[priv->pvid[port]];
  841.         if (priv->chip_data.ar8216.vlan_tagged & BIT(port))
  842.             egress = AR8216_OUT_ADD_VLAN;
  843.         else
  844.             egress = AR8216_OUT_STRIP_VLAN;
  845.         ingress = AR8216_IN_SECURE;
  846.     } else {
  847.         pvid = port;
  848.         egress = AR8216_OUT_KEEP;
  849.         ingress = AR8216_IN_PORT_ONLY;
  850.     }
  851.  
  852.     ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
  853.            AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
  854.            AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
  855.            AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
  856.            AR8216_PORT_CTRL_LEARN |
  857.            (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
  858.            (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
  859.  
  860.     ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
  861.            AR8236_PORT_VLAN_DEFAULT_ID,
  862.            (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
  863.  
  864.     ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
  865.            AR8236_PORT_VLAN2_VLAN_MODE |
  866.            AR8236_PORT_VLAN2_MEMBER,
  867.            (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
  868.            (members << AR8236_PORT_VLAN2_MEMBER_S));
  869. }
  870.  
  871. static int
  872. ar8236_hw_init(struct ar8xxx_priv *priv)
  873. {
  874.     int i;
  875.     struct mii_bus *bus;
  876.  
  877.     if (priv->initialized)
  878.         return 0;
  879.  
  880.     /* Initialize the PHYs */
  881.     bus = priv->mii_bus;
  882.     for (i = 0; i < 5; i++) {
  883.         mdiobus_write(bus, i, MII_ADVERTISE,
  884.                   ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
  885.                   ADVERTISE_PAUSE_ASYM);
  886.         mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
  887.     }
  888.     msleep(1000);
  889.  
  890.     priv->initialized = true;
  891.     return 0;
  892. }
  893.  
  894. static void
  895. ar8236_init_globals(struct ar8xxx_priv *priv)
  896. {
  897.     /* enable jumbo frames */
  898.     ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
  899.            AR8316_GCTRL_MTU, 9018 + 8 + 2);
  900.  
  901.     /* Enable MIB counters */
  902.     ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
  903.            (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
  904.            AR8236_MIB_EN);
  905. }
  906.  
  907. static const struct ar8xxx_chip ar8236_chip = {
  908.     .caps = AR8XXX_CAP_MIB_COUNTERS,
  909.     .hw_init = ar8236_hw_init,
  910.     .init_globals = ar8236_init_globals,
  911.     .init_port = ar8216_init_port,
  912.     .setup_port = ar8236_setup_port,
  913.     .read_port_status = ar8216_read_port_status,
  914.     .atu_flush = ar8216_atu_flush,
  915.     .vtu_flush = ar8216_vtu_flush,
  916.     .vtu_load_vlan = ar8216_vtu_load_vlan,
  917.  
  918.     .num_mibs = ARRAY_SIZE(ar8236_mibs),
  919.     .mib_decs = ar8236_mibs,
  920. };
  921.  
  922. static int
  923. ar8316_hw_init(struct ar8xxx_priv *priv)
  924. {
  925.     int i;
  926.     u32 val, newval;
  927.     struct mii_bus *bus;
  928.  
  929.     val = priv->read(priv, AR8316_REG_POSTRIP);
  930.  
  931.     if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
  932.         if (priv->port4_phy) {
  933.             /* value taken from Ubiquiti RouterStation Pro */
  934.             newval = 0x81461bea;
  935.             pr_info("ar8316: Using port 4 as PHY\n");
  936.         } else {
  937.             newval = 0x01261be2;
  938.             pr_info("ar8316: Using port 4 as switch port\n");
  939.         }
  940.     } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
  941.         /* value taken from AVM Fritz!Box 7390 sources */
  942.         newval = 0x010e5b71;
  943.     } else {
  944.         /* no known value for phy interface */
  945.         pr_err("ar8316: unsupported mii mode: %d.\n",
  946.                priv->phy->interface);
  947.         return -EINVAL;
  948.     }
  949.  
  950.     if (val == newval)
  951.         goto out;
  952.  
  953.     priv->write(priv, AR8316_REG_POSTRIP, newval);
  954.  
  955.     if (priv->port4_phy &&
  956.         priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
  957.         /* work around for phy4 rgmii mode */
  958.         ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
  959.         /* rx delay */
  960.         ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
  961.         /* tx delay */
  962.         ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
  963.         msleep(1000);
  964.     }
  965.  
  966.     /* Initialize the ports */
  967.     bus = priv->mii_bus;
  968.     for (i = 0; i < 5; i++) {
  969.         /* initialize the port itself */
  970.         mdiobus_write(bus, i, MII_ADVERTISE,
  971.             ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  972.         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
  973.         mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
  974.     }
  975.  
  976.     msleep(1000);
  977.  
  978. out:
  979.     priv->initialized = true;
  980.     return 0;
  981. }
  982.  
  983. static void
  984. ar8316_init_globals(struct ar8xxx_priv *priv)
  985. {
  986.     /* standard atheros magic */
  987.     priv->write(priv, 0x38, 0xc000050e);
  988.  
  989.     /* enable cpu port to receive multicast and broadcast frames */
  990.     priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
  991.  
  992.     /* enable jumbo frames */
  993.     ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
  994.            AR8316_GCTRL_MTU, 9018 + 8 + 2);
  995.  
  996.     /* Enable MIB counters */
  997.     ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
  998.            (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
  999.            AR8236_MIB_EN);
  1000. }
  1001.  
  1002. static const struct ar8xxx_chip ar8316_chip = {
  1003.     .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
  1004.     .hw_init = ar8316_hw_init,
  1005.     .init_globals = ar8316_init_globals,
  1006.     .init_port = ar8216_init_port,
  1007.     .setup_port = ar8216_setup_port,
  1008.     .read_port_status = ar8216_read_port_status,
  1009.     .atu_flush = ar8216_atu_flush,
  1010.     .vtu_flush = ar8216_vtu_flush,
  1011.     .vtu_load_vlan = ar8216_vtu_load_vlan,
  1012.  
  1013.     .num_mibs = ARRAY_SIZE(ar8236_mibs),
  1014.     .mib_decs = ar8236_mibs,
  1015. };
  1016.  
  1017. static u32
  1018. ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
  1019. {
  1020.     u32 t;
  1021.  
  1022.     if (!cfg)
  1023.         return 0;
  1024.  
  1025.     t = 0;
  1026.     switch (cfg->mode) {
  1027.     case AR8327_PAD_NC:
  1028.         break;
  1029.  
  1030.     case AR8327_PAD_MAC2MAC_MII:
  1031.         t = AR8327_PAD_MAC_MII_EN;
  1032.         if (cfg->rxclk_sel)
  1033.             t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
  1034.         if (cfg->txclk_sel)
  1035.             t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
  1036.         break;
  1037.  
  1038.     case AR8327_PAD_MAC2MAC_GMII:
  1039.         t = AR8327_PAD_MAC_GMII_EN;
  1040.         if (cfg->rxclk_sel)
  1041.             t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
  1042.         if (cfg->txclk_sel)
  1043.             t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
  1044.         break;
  1045.  
  1046.     case AR8327_PAD_MAC_SGMII:
  1047.         t = AR8327_PAD_SGMII_EN;
  1048.  
  1049.         /*
  1050.          * WAR for the QUalcomm Atheros AP136 board.
  1051.          * It seems that RGMII TX/RX delay settings needs to be
  1052.          * applied for SGMII mode as well, The ethernet is not
  1053.          * reliable without this.
  1054.          */
  1055.         t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
  1056.         t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
  1057.         if (cfg->rxclk_delay_en)
  1058.             t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
  1059.         if (cfg->txclk_delay_en)
  1060.             t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
  1061.  
  1062.         if (cfg->sgmii_delay_en)
  1063.             t |= AR8327_PAD_SGMII_DELAY_EN;
  1064.  
  1065.         break;
  1066.  
  1067.     case AR8327_PAD_MAC2PHY_MII:
  1068.         t = AR8327_PAD_PHY_MII_EN;
  1069.         if (cfg->rxclk_sel)
  1070.             t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
  1071.         if (cfg->txclk_sel)
  1072.             t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
  1073.         break;
  1074.  
  1075.     case AR8327_PAD_MAC2PHY_GMII:
  1076.         t = AR8327_PAD_PHY_GMII_EN;
  1077.         if (cfg->pipe_rxclk_sel)
  1078.             t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
  1079.         if (cfg->rxclk_sel)
  1080.             t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
  1081.         if (cfg->txclk_sel)
  1082.             t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
  1083.         break;
  1084.  
  1085.     case AR8327_PAD_MAC_RGMII:
  1086.         t = AR8327_PAD_RGMII_EN;
  1087.         t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
  1088.         t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
  1089.         if (cfg->rxclk_delay_en)
  1090.             t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
  1091.         if (cfg->txclk_delay_en)
  1092.             t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
  1093.         break;
  1094.  
  1095.     case AR8327_PAD_PHY_GMII:
  1096.         t = AR8327_PAD_PHYX_GMII_EN;
  1097.         break;
  1098.  
  1099.     case AR8327_PAD_PHY_RGMII:
  1100.         t = AR8327_PAD_PHYX_RGMII_EN;
  1101.         break;
  1102.  
  1103.     case AR8327_PAD_PHY_MII:
  1104.         t = AR8327_PAD_PHYX_MII_EN;
  1105.         break;
  1106.     }
  1107.  
  1108.     return t;
  1109. }
  1110.  
  1111. static void
  1112. ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
  1113. {
  1114.     switch (priv->chip_rev) {
  1115.     case 1:
  1116.         /* For 100M waveform */
  1117.         ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
  1118.         /* Turn on Gigabit clock */
  1119.         ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
  1120.         break;
  1121.  
  1122.     case 2:
  1123.         ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
  1124.         ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
  1125.         /* fallthrough */
  1126.     case 4:
  1127.         ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
  1128.         ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
  1129.  
  1130.         ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
  1131.         ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
  1132.         ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
  1133.         break;
  1134.     }
  1135. }
  1136.  
  1137. static u32
  1138. ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
  1139. {
  1140.     u32 t;
  1141.  
  1142.     if (!cfg->force_link)
  1143.         return AR8216_PORT_STATUS_LINK_AUTO;
  1144.  
  1145.     t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
  1146.     t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
  1147.     t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
  1148.     t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
  1149.  
  1150.     switch (cfg->speed) {
  1151.     case AR8327_PORT_SPEED_10:
  1152.         t |= AR8216_PORT_SPEED_10M;
  1153.         break;
  1154.     case AR8327_PORT_SPEED_100:
  1155.         t |= AR8216_PORT_SPEED_100M;
  1156.         break;
  1157.     case AR8327_PORT_SPEED_1000:
  1158.         t |= AR8216_PORT_SPEED_1000M;
  1159.         break;
  1160.     }
  1161.  
  1162.     return t;
  1163. }
  1164.  
  1165. #define AR8327_LED_ENTRY(_num, _reg, _shift) \
  1166.     [_num] = { .reg = (_reg), .shift = (_shift) }
  1167.  
  1168. static const struct ar8327_led_entry
  1169. ar8327_led_map[AR8327_NUM_LEDS] = {
  1170.     AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
  1171.     AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
  1172.     AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
  1173.  
  1174.     AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
  1175.     AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
  1176.     AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
  1177.  
  1178.     AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
  1179.     AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
  1180.     AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
  1181.  
  1182.     AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
  1183.     AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
  1184.     AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
  1185.  
  1186.     AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
  1187.     AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
  1188.     AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
  1189. };
  1190.  
  1191. static void
  1192. ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
  1193.                enum ar8327_led_pattern pattern)
  1194. {
  1195.     const struct ar8327_led_entry *entry;
  1196.  
  1197.     entry = &ar8327_led_map[led_num];
  1198.     ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
  1199.            (3 << entry->shift), pattern << entry->shift);
  1200. }
  1201.  
  1202. static void
  1203. ar8327_led_work_func(struct work_struct *work)
  1204. {
  1205.     struct ar8327_led *aled;
  1206.     u8 pattern;
  1207.  
  1208.     aled = container_of(work, struct ar8327_led, led_work);
  1209.  
  1210.     spin_lock(&aled->lock);
  1211.     pattern = aled->pattern;
  1212.     spin_unlock(&aled->lock);
  1213.  
  1214.     ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
  1215.                    pattern);
  1216. }
  1217.  
  1218. static void
  1219. ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
  1220. {
  1221.     if (aled->pattern == pattern)
  1222.         return;
  1223.  
  1224.     aled->pattern = pattern;
  1225.     schedule_work(&aled->led_work);
  1226. }
  1227.  
  1228. static inline struct ar8327_led *
  1229. led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
  1230. {
  1231.     return container_of(led_cdev, struct ar8327_led, cdev);
  1232. }
  1233.  
  1234. static int
  1235. ar8327_led_blink_set(struct led_classdev *led_cdev,
  1236.              unsigned long *delay_on,
  1237.              unsigned long *delay_off)
  1238. {
  1239.     struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
  1240.  
  1241.     if (*delay_on == 0 && *delay_off == 0) {
  1242.         *delay_on = 125;
  1243.         *delay_off = 125;
  1244.     }
  1245.  
  1246.     if (*delay_on != 125 || *delay_off != 125) {
  1247.         /*
  1248.          * The hardware only supports blinking at 4Hz. Fall back
  1249.          * to software implementation in other cases.
  1250.          */
  1251.         return -EINVAL;
  1252.     }
  1253.  
  1254.     spin_lock(&aled->lock);
  1255.  
  1256.     aled->enable_hw_mode = false;
  1257.     ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
  1258.  
  1259.     spin_unlock(&aled->lock);
  1260.  
  1261.     return 0;
  1262. }
  1263.  
  1264. static void
  1265. ar8327_led_set_brightness(struct led_classdev *led_cdev,
  1266.               enum led_brightness brightness)
  1267. {
  1268.     struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
  1269.     u8 pattern;
  1270.     bool active;
  1271.  
  1272.     active = (brightness != LED_OFF);
  1273.     active ^= aled->active_low;
  1274.  
  1275.     pattern = (active) ? AR8327_LED_PATTERN_ON :
  1276.                  AR8327_LED_PATTERN_OFF;
  1277.  
  1278.     spin_lock(&aled->lock);
  1279.  
  1280.     aled->enable_hw_mode = false;
  1281.     ar8327_led_schedule_change(aled, pattern);
  1282.  
  1283.     spin_unlock(&aled->lock);
  1284. }
  1285.  
  1286. static ssize_t
  1287. ar8327_led_enable_hw_mode_show(struct device *dev,
  1288.                    struct device_attribute *attr,
  1289.                    char *buf)
  1290. {
  1291.     struct led_classdev *led_cdev = dev_get_drvdata(dev);
  1292.     struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
  1293.     ssize_t ret = 0;
  1294.  
  1295.     spin_lock(&aled->lock);
  1296.     ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
  1297.     spin_unlock(&aled->lock);
  1298.  
  1299.     return ret;
  1300. }
  1301.  
  1302. static ssize_t
  1303. ar8327_led_enable_hw_mode_store(struct device *dev,
  1304.                 struct device_attribute *attr,
  1305.                 const char *buf,
  1306.                 size_t size)
  1307. {
  1308.         struct led_classdev *led_cdev = dev_get_drvdata(dev);
  1309.     struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
  1310.     u8 pattern;
  1311.     u8 value;
  1312.     int ret;
  1313.  
  1314.     ret = kstrtou8(buf, 10, &value);
  1315.     if (ret < 0)
  1316.         return -EINVAL;
  1317.  
  1318.     spin_lock(&aled->lock);
  1319.  
  1320.     aled->enable_hw_mode = !!value;
  1321.     if (aled->enable_hw_mode)
  1322.         pattern = AR8327_LED_PATTERN_RULE;
  1323.     else
  1324.         pattern = AR8327_LED_PATTERN_OFF;
  1325.  
  1326.     ar8327_led_schedule_change(aled, pattern);
  1327.  
  1328.     spin_unlock(&aled->lock);
  1329.  
  1330.     return size;
  1331. }
  1332.  
  1333. static DEVICE_ATTR(enable_hw_mode,  S_IRUGO | S_IWUSR,
  1334.            ar8327_led_enable_hw_mode_show,
  1335.            ar8327_led_enable_hw_mode_store);
  1336.  
  1337. static int
  1338. ar8327_led_register(struct ar8xxx_priv *priv, struct ar8327_led *aled)
  1339. {
  1340.     int ret;
  1341.  
  1342.     ret = led_classdev_register(NULL, &aled->cdev);
  1343.     if (ret < 0)
  1344.         return ret;
  1345.  
  1346.     if (aled->mode == AR8327_LED_MODE_HW) {
  1347.         ret = device_create_file(aled->cdev.dev,
  1348.                      &dev_attr_enable_hw_mode);
  1349.         if (ret)
  1350.             goto err_unregister;
  1351.     }
  1352.  
  1353.     return 0;
  1354.  
  1355. err_unregister:
  1356.     led_classdev_unregister(&aled->cdev);
  1357.     return ret;
  1358. }
  1359.  
  1360. static void
  1361. ar8327_led_unregister(struct ar8327_led *aled)
  1362. {
  1363.     if (aled->mode == AR8327_LED_MODE_HW)
  1364.         device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
  1365.  
  1366.     led_classdev_unregister(&aled->cdev);
  1367.     cancel_work_sync(&aled->led_work);
  1368. }
  1369.  
  1370. static int
  1371. ar8327_led_create(struct ar8xxx_priv *priv,
  1372.           const struct ar8327_led_info *led_info)
  1373. {
  1374.     struct ar8327_data *data = &priv->chip_data.ar8327;
  1375.     struct ar8327_led *aled;
  1376.     int ret;
  1377.  
  1378.     if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
  1379.         return 0;
  1380.  
  1381.     if (!led_info->name)
  1382.         return -EINVAL;
  1383.  
  1384.     if (led_info->led_num >= AR8327_NUM_LEDS)
  1385.         return -EINVAL;
  1386.  
  1387.     aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
  1388.                GFP_KERNEL);
  1389.     if (!aled)
  1390.         return -ENOMEM;
  1391.  
  1392.     aled->sw_priv = priv;
  1393.     aled->led_num = led_info->led_num;
  1394.     aled->active_low = led_info->active_low;
  1395.     aled->mode = led_info->mode;
  1396.  
  1397.     if (aled->mode == AR8327_LED_MODE_HW)
  1398.         aled->enable_hw_mode = true;
  1399.  
  1400.     aled->name = (char *)(aled + 1);
  1401.     strcpy(aled->name, led_info->name);
  1402.  
  1403.     aled->cdev.name = aled->name;
  1404.     aled->cdev.brightness_set = ar8327_led_set_brightness;
  1405.     aled->cdev.blink_set = ar8327_led_blink_set;
  1406.     aled->cdev.default_trigger = led_info->default_trigger;
  1407.  
  1408.     spin_lock_init(&aled->lock);
  1409.     mutex_init(&aled->mutex);
  1410.     INIT_WORK(&aled->led_work, ar8327_led_work_func);
  1411.  
  1412.     ret = ar8327_led_register(priv, aled);
  1413.     if (ret)
  1414.         goto err_free;
  1415.  
  1416.     data->leds[data->num_leds++] = aled;
  1417.  
  1418.     return 0;
  1419.  
  1420. err_free:
  1421.     kfree(aled);
  1422.     return ret;
  1423. }
  1424.  
  1425. static void
  1426. ar8327_led_destroy(struct ar8327_led *aled)
  1427. {
  1428.     ar8327_led_unregister(aled);
  1429.     kfree(aled);
  1430. }
  1431.  
  1432. static void
  1433. ar8327_leds_init(struct ar8xxx_priv *priv)
  1434. {
  1435.     struct ar8327_data *data;
  1436.     unsigned i;
  1437.  
  1438.     if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
  1439.         return;
  1440.  
  1441.     data = &priv->chip_data.ar8327;
  1442.  
  1443.     for (i = 0; i < data->num_leds; i++) {
  1444.         struct ar8327_led *aled;
  1445.  
  1446.         aled = data->leds[i];
  1447.  
  1448.         if (aled->enable_hw_mode)
  1449.             aled->pattern = AR8327_LED_PATTERN_RULE;
  1450.         else
  1451.             aled->pattern = AR8327_LED_PATTERN_OFF;
  1452.  
  1453.         ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
  1454.     }
  1455. }
  1456.  
  1457. static void
  1458. ar8327_leds_cleanup(struct ar8xxx_priv *priv)
  1459. {
  1460.     struct ar8327_data *data = &priv->chip_data.ar8327;
  1461.     unsigned i;
  1462.  
  1463.     if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
  1464.         return;
  1465.  
  1466.     for (i = 0; i < data->num_leds; i++) {
  1467.         struct ar8327_led *aled;
  1468.  
  1469.         aled = data->leds[i];
  1470.         ar8327_led_destroy(aled);
  1471.     }
  1472.  
  1473.     kfree(data->leds);
  1474. }
  1475.  
  1476. static int
  1477. ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
  1478.                struct ar8327_platform_data *pdata)
  1479. {
  1480.     struct ar8327_led_cfg *led_cfg;
  1481.     struct ar8327_data *data;
  1482.     u32 pos, new_pos;
  1483.     u32 t;
  1484.  
  1485.     if (!pdata)
  1486.         return -EINVAL;
  1487.  
  1488.     priv->get_port_link = pdata->get_port_link;
  1489.  
  1490.     data = &priv->chip_data.ar8327;
  1491.  
  1492.     data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
  1493.     data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
  1494.  
  1495.     t = ar8327_get_pad_cfg(pdata->pad0_cfg);
  1496.     if (chip_is_ar8337(priv))
  1497.         t |= AR8337_PAD_MAC06_EXCHANGE_EN;
  1498.  
  1499.     priv->write(priv, AR8327_REG_PAD0_MODE, t);
  1500.     t = ar8327_get_pad_cfg(pdata->pad5_cfg);
  1501.     priv->write(priv, AR8327_REG_PAD5_MODE, t);
  1502.     t = ar8327_get_pad_cfg(pdata->pad6_cfg);
  1503.     priv->write(priv, AR8327_REG_PAD6_MODE, t);
  1504.  
  1505.     pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
  1506.     new_pos = pos;
  1507.  
  1508.     led_cfg = pdata->led_cfg;
  1509.     if (led_cfg) {
  1510.         if (led_cfg->open_drain)
  1511.             new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
  1512.         else
  1513.             new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
  1514.  
  1515.         priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
  1516.         priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
  1517.         priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
  1518.         priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
  1519.  
  1520.         if (new_pos != pos)
  1521.             new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
  1522.     }
  1523.  
  1524.     if (pdata->sgmii_cfg) {
  1525.         t = pdata->sgmii_cfg->sgmii_ctrl;
  1526.         if (priv->chip_rev == 1)
  1527.             t |= AR8327_SGMII_CTRL_EN_PLL |
  1528.                  AR8327_SGMII_CTRL_EN_RX |
  1529.                  AR8327_SGMII_CTRL_EN_TX;
  1530.         else
  1531.             t &= ~(AR8327_SGMII_CTRL_EN_PLL |
  1532.                    AR8327_SGMII_CTRL_EN_RX |
  1533.                    AR8327_SGMII_CTRL_EN_TX);
  1534.  
  1535.         priv->write(priv, AR8327_REG_SGMII_CTRL, t);
  1536.  
  1537.         if (pdata->sgmii_cfg->serdes_aen)
  1538.             new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
  1539.         else
  1540.             new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
  1541.     }
  1542.  
  1543.     priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
  1544.  
  1545.     if (pdata->leds && pdata->num_leds) {
  1546.         int i;
  1547.  
  1548.         data->leds = kzalloc(pdata->num_leds * sizeof(void *),
  1549.                      GFP_KERNEL);
  1550.         if (!data->leds)
  1551.             return -ENOMEM;
  1552.  
  1553.         for (i = 0; i < pdata->num_leds; i++)
  1554.             ar8327_led_create(priv, &pdata->leds[i]);
  1555.     }
  1556.  
  1557.     return 0;
  1558. }
  1559.  
  1560. #ifdef CONFIG_OF
  1561. static int
  1562. ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
  1563. {
  1564.     const __be32 *paddr;
  1565.     int len;
  1566.     int i;
  1567.  
  1568.     paddr = of_get_property(np, "qca,ar8327-initvals", &len);
  1569.     if (!paddr || len < (2 * sizeof(*paddr)))
  1570.         return -EINVAL;
  1571.  
  1572.     len /= sizeof(*paddr);
  1573.  
  1574.     for (i = 0; i < len - 1; i += 2) {
  1575.         u32 reg;
  1576.         u32 val;
  1577.  
  1578.         reg = be32_to_cpup(paddr + i);
  1579.         val = be32_to_cpup(paddr + i + 1);
  1580.  
  1581.         switch (reg) {
  1582.         case AR8327_REG_PORT_STATUS(0):
  1583.             priv->chip_data.ar8327.port0_status = val;
  1584.             break;
  1585.         case AR8327_REG_PORT_STATUS(6):
  1586.             priv->chip_data.ar8327.port6_status = val;
  1587.             break;
  1588.         default:
  1589.             priv->write(priv, reg, val);
  1590.             break;
  1591.         }
  1592.     }
  1593.  
  1594.     return 0;
  1595. }
  1596. #else
  1597. static inline int
  1598. ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
  1599. {
  1600.     return -EINVAL;
  1601. }
  1602. #endif
  1603.  
  1604. static int
  1605. ar8327_hw_init(struct ar8xxx_priv *priv)
  1606. {
  1607.     struct mii_bus *bus;
  1608.     int ret;
  1609.     int i;
  1610.  
  1611.     if (priv->phy->dev.of_node)
  1612.         ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
  1613.     else
  1614.         ret = ar8327_hw_config_pdata(priv,
  1615.                          priv->phy->dev.platform_data);
  1616.  
  1617.     if (ret)
  1618.         return ret;
  1619.  
  1620.     ar8327_leds_init(priv);
  1621.  
  1622.     bus = priv->mii_bus;
  1623.     for (i = 0; i < AR8327_NUM_PHYS; i++) {
  1624.         ar8327_phy_fixup(priv, i);
  1625.  
  1626.         /* start aneg on the PHY */
  1627.         mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
  1628.                              ADVERTISE_PAUSE_CAP |
  1629.                              ADVERTISE_PAUSE_ASYM);
  1630.         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
  1631.         mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
  1632.     }
  1633.  
  1634.     msleep(1000);
  1635.  
  1636.     return 0;
  1637. }
  1638.  
  1639. static void
  1640. ar8327_cleanup(struct ar8xxx_priv *priv)
  1641. {
  1642.     ar8327_leds_cleanup(priv);
  1643. }
  1644.  
  1645. static void
  1646. ar8327_init_globals(struct ar8xxx_priv *priv)
  1647. {
  1648.     u32 t;
  1649.  
  1650.     /* enable CPU port and disable mirror port */
  1651.     t = AR8327_FWD_CTRL0_CPU_PORT_EN |
  1652.         AR8327_FWD_CTRL0_MIRROR_PORT;
  1653.     priv->write(priv, AR8327_REG_FWD_CTRL0, t);
  1654.  
  1655.     /* forward multicast and broadcast frames to CPU */
  1656.     t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
  1657.         (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
  1658.         (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
  1659.     priv->write(priv, AR8327_REG_FWD_CTRL1, t);
  1660.  
  1661.     /* enable jumbo frames */
  1662.     ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
  1663.            AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
  1664.  
  1665.     /* Enable MIB counters */
  1666.     ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
  1667.                AR8327_MODULE_EN_MIB);
  1668. }
  1669.  
  1670. static void
  1671. ar8327_init_port(struct ar8xxx_priv *priv, int port)
  1672. {
  1673.     u32 t;
  1674.  
  1675.     if (port == AR8216_PORT_CPU)
  1676.         t = priv->chip_data.ar8327.port0_status;
  1677.     else if (port == 6)
  1678.         t = priv->chip_data.ar8327.port6_status;
  1679.     else
  1680.         t = AR8216_PORT_STATUS_LINK_AUTO;
  1681.  
  1682.     priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
  1683.     priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
  1684.  
  1685.     t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
  1686.     t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
  1687.     priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
  1688.  
  1689.     t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
  1690.     priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
  1691.  
  1692.     t = AR8327_PORT_LOOKUP_LEARN;
  1693.     t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
  1694.     priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
  1695. }
  1696.  
  1697. static u32
  1698. ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
  1699. {
  1700.     return priv->read(priv, AR8327_REG_PORT_STATUS(port));
  1701. }
  1702.  
  1703. static int
  1704. ar8327_atu_flush(struct ar8xxx_priv *priv)
  1705. {
  1706.     int ret;
  1707.  
  1708.     ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
  1709.                   AR8327_ATU_FUNC_BUSY, 0);
  1710.     if (!ret)
  1711.         priv->write(priv, AR8327_REG_ATU_FUNC,
  1712.                 AR8327_ATU_FUNC_OP_FLUSH);
  1713.  
  1714.     return ret;
  1715. }
  1716.  
  1717. static void
  1718. ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
  1719. {
  1720.     if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
  1721.                 AR8327_VTU_FUNC1_BUSY, 0))
  1722.         return;
  1723.  
  1724.     if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
  1725.         priv->write(priv, AR8327_REG_VTU_FUNC0, val);
  1726.  
  1727.     op |= AR8327_VTU_FUNC1_BUSY;
  1728.     priv->write(priv, AR8327_REG_VTU_FUNC1, op);
  1729. }
  1730.  
  1731. static void
  1732. ar8327_vtu_flush(struct ar8xxx_priv *priv)
  1733. {
  1734.     ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
  1735. }
  1736.  
  1737. static void
  1738. ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vlan)
  1739. {
  1740.     u32 op, val;
  1741.     int i;
  1742.    
  1743.     u32 vid = priv->vlan_id[vlan];
  1744.     u32 port_mask = priv->vlan_table[vlan];
  1745.     u32 tagged = priv->chip_data.ar8327.vlan_tagged[vlan];
  1746.    
  1747.    
  1748.     op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
  1749.     val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
  1750.     for (i = 0; i < AR8327_NUM_PORTS; i++) {
  1751.         u32 mode;
  1752.  
  1753.         if ((port_mask & BIT(i)) == 0)
  1754.             mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
  1755.         else if (priv->vlan == 0)
  1756.             mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
  1757.         else if (tagged & BIT(i))
  1758.             mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
  1759.         else
  1760.             mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
  1761.  
  1762.         val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
  1763.     }
  1764.     ar8327_vtu_op(priv, op, val);
  1765. }
  1766.  
  1767. static void
  1768. ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
  1769. {
  1770.     u32 ingress, mode;
  1771.     u32 pvid;  
  1772.  
  1773.     u32 t;
  1774.    
  1775.     if (priv->vlan) {
  1776.         pvid = priv->vlan_id[priv->pvid[port]];
  1777.         mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
  1778.         ingress = AR8216_IN_SECURE;
  1779.     } else {
  1780.         pvid = port;
  1781.         mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
  1782.         ingress = AR8216_IN_PORT_ONLY;
  1783.     }
  1784.  
  1785.     t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
  1786.     t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
  1787.     priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
  1788.  
  1789.     t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
  1790.     t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
  1791.     priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
  1792.  
  1793.     t = members;
  1794.     t |= AR8327_PORT_LOOKUP_LEARN;
  1795.     t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
  1796.     t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
  1797.     priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
  1798. }
  1799.  
  1800. static const struct ar8xxx_chip ar8327_chip = {
  1801.     .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
  1802.     .hw_init = ar8327_hw_init,
  1803.     .cleanup = ar8327_cleanup,
  1804.     .init_globals = ar8327_init_globals,
  1805.     .init_port = ar8327_init_port,
  1806.     .setup_port = ar8327_setup_port,
  1807.     .read_port_status = ar8327_read_port_status,
  1808.     .atu_flush = ar8327_atu_flush,
  1809.     .vtu_flush = ar8327_vtu_flush,
  1810.     .vtu_load_vlan = ar8327_vtu_load_vlan,
  1811.  
  1812.     .num_mibs = ARRAY_SIZE(ar8236_mibs),
  1813.     .mib_decs = ar8236_mibs,
  1814. };
  1815.  
  1816. static int
  1817. ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
  1818.            struct switch_val *val)
  1819. {
  1820.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1821.     priv->vlan = !!val->value.i;
  1822.     return 0;
  1823. }
  1824.  
  1825. static int
  1826. ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
  1827.            struct switch_val *val)
  1828. {
  1829.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1830.     val->value.i = priv->vlan;
  1831.     return 0;
  1832. }
  1833.  
  1834.  
  1835. static int
  1836. ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
  1837. {
  1838.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1839.  
  1840.     /* make sure no invalid PVIDs get set */
  1841.  
  1842.     if (vlan >= dev->vlans)
  1843.         return -EINVAL;
  1844.  
  1845.     priv->pvid[port] = vlan;
  1846.     return 0;
  1847. }
  1848.  
  1849. static int
  1850. ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
  1851. {
  1852.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1853.     *vlan = priv->pvid[port];
  1854.     return 0;
  1855. }
  1856.  
  1857. static int
  1858. ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
  1859.           struct switch_val *val)
  1860. {
  1861.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1862.     priv->vlan_id[val->port_vlan] = val->value.i;
  1863.     return 0;
  1864. }
  1865.  
  1866. static int
  1867. ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
  1868.           struct switch_val *val)
  1869. {
  1870.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1871.     val->value.i = priv->vlan_id[val->port_vlan];
  1872.     return 0;
  1873. }
  1874.  
  1875. static int
  1876. ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
  1877.             struct switch_port_link *link)
  1878. {
  1879.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1880.  
  1881.     ar8216_read_port_link(priv, port, link);
  1882.     return 0;
  1883. }
  1884.  
  1885. static int
  1886. ar8xxx_sw_get_ports(struct switch_val *val, int ports, u8 port_mask, u8 tagged)
  1887. {
  1888.     int i;
  1889.     val->len = 0;
  1890.     for (i = 0; i < ports; i++) {
  1891.         struct switch_port *p;
  1892.  
  1893.         if (!(port_mask & BIT(i)))
  1894.             continue;
  1895.  
  1896.         p = &val->value.ports[val->len++];
  1897.         p->id = i;
  1898.         if (tagged & BIT(i))
  1899.             p->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
  1900.         else
  1901.             p->flags = 0;
  1902.     }
  1903.     return 0;
  1904. }
  1905.  
  1906. static int
  1907. ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
  1908. {
  1909.     int ports = dev->ports;
  1910.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1911.     u8 port_mask = priv->vlan_table[val->port_vlan];
  1912.     u8 tagged = priv->chip_data.ar8216.vlan_tagged;
  1913.    
  1914.     return ar8xxx_sw_get_ports(val, ports, port_mask, tagged);
  1915. }
  1916.  
  1917. static int
  1918. ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
  1919. {
  1920.     int ports = dev->ports;
  1921.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1922.     u8 port_mask = priv->vlan_table[val->port_vlan];
  1923.     u8 tagged = priv->chip_data.ar8327.vlan_tagged[val->port_vlan];
  1924.    
  1925.     return ar8xxx_sw_get_ports(val, ports, port_mask, tagged);
  1926. }
  1927.  
  1928. static int
  1929. ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
  1930. {
  1931.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1932.     u8 *vt = &priv->vlan_table[val->port_vlan];
  1933.     u8 *tagged = &priv->chip_data.ar8216.vlan_tagged;
  1934.    
  1935.     int i, j;
  1936.  
  1937.     *vt = 0;
  1938.     for (i = 0; i < val->len; i++) {
  1939.         struct switch_port *p = &val->value.ports[i];
  1940.  
  1941.         if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED)) {
  1942.            
  1943.             /* if port was untagged before then
  1944.              * remove him from other vlans */
  1945.             if(*tagged & BIT(p->id)){
  1946.                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
  1947.                     if (j == val->port_vlan)
  1948.                         continue;
  1949.                
  1950.                     priv->vlan_table[j] &= ~(BIT(p->id));
  1951.                 }
  1952.             }
  1953.            
  1954.             *tagged |= BIT(p->id);
  1955.         } else {
  1956.             *tagged &= ~(BIT(p->id));
  1957.             priv->pvid[p->id] = val->port_vlan;
  1958.            
  1959.             /* make sure that an untagged port does not
  1960.             * appear in other vlans */
  1961.             for (j = 0; j < AR8X16_MAX_VLANS; j++) {
  1962.                 if (j == val->port_vlan)
  1963.                     continue;
  1964.                
  1965.                 priv->vlan_table[j] &= ~(BIT(p->id));
  1966.             }
  1967.         }
  1968.  
  1969.         *vt |= BIT(p->id);
  1970.     }
  1971.     return 0;
  1972. }
  1973.  
  1974. static int
  1975. ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
  1976. {
  1977.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1978.     u8 *vt = &priv->vlan_table[val->port_vlan];
  1979.     u8 *vlan_tagged = priv->chip_data.ar8327.vlan_tagged;
  1980.     u8 *tagged = &vlan_tagged[val->port_vlan];
  1981.    
  1982.     int i, j;
  1983.  
  1984.     *vt = 0;
  1985.     *tagged = 0;
  1986.     for (i = 0; i < val->len; i++) {
  1987.         struct switch_port *p = &val->value.ports[i];
  1988.  
  1989.         if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED)) {
  1990.             *tagged |= BIT(p->id);
  1991.         } else {
  1992.             priv->pvid[p->id] = val->port_vlan;
  1993.            
  1994.             /* make sure that an untagged port does not
  1995.             * appear in other vlans */
  1996.             for (j = 0; j < AR8X16_MAX_VLANS; j++) {
  1997.                 if (j == val->port_vlan)
  1998.                     continue;
  1999.                
  2000.                 // skip tagged
  2001.                 if(vlan_tagged[j] & BIT(SWITCH_PORT_FLAG_TAGGED))
  2002.                     continue;
  2003.                
  2004.                 // remove port
  2005.                 priv->vlan_table[j] &= ~(BIT(p->id));
  2006.             }
  2007.         }
  2008.  
  2009.         *vt |= BIT(p->id);
  2010.     }
  2011.     return 0;
  2012. }
  2013.  
  2014. static void
  2015. ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
  2016. {
  2017.     int port;
  2018.  
  2019.     /* reset all mirror registers */
  2020.     ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
  2021.            AR8327_FWD_CTRL0_MIRROR_PORT,
  2022.            (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
  2023.     for (port = 0; port < AR8327_NUM_PORTS; port++) {
  2024.         ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
  2025.                AR8327_PORT_LOOKUP_ING_MIRROR_EN,
  2026.                0);
  2027.  
  2028.         ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
  2029.                AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
  2030.                0);
  2031.     }
  2032.  
  2033.     /* now enable mirroring if necessary */
  2034.     if (priv->source_port >= AR8327_NUM_PORTS ||
  2035.         priv->monitor_port >= AR8327_NUM_PORTS ||
  2036.         priv->source_port == priv->monitor_port) {
  2037.         return;
  2038.     }
  2039.  
  2040.     ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
  2041.            AR8327_FWD_CTRL0_MIRROR_PORT,
  2042.            (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
  2043.  
  2044.     if (priv->mirror_rx)
  2045.         ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
  2046.                AR8327_PORT_LOOKUP_ING_MIRROR_EN,
  2047.                AR8327_PORT_LOOKUP_ING_MIRROR_EN);
  2048.  
  2049.     if (priv->mirror_tx)
  2050.         ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
  2051.                AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
  2052.                AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
  2053. }
  2054.  
  2055. static void
  2056. ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
  2057. {
  2058.     int port;
  2059.  
  2060.     /* reset all mirror registers */
  2061.     ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
  2062.            AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
  2063.            (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
  2064.     for (port = 0; port < AR8216_NUM_PORTS; port++) {
  2065.         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
  2066.                AR8216_PORT_CTRL_MIRROR_RX,
  2067.                0);
  2068.  
  2069.         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
  2070.                AR8216_PORT_CTRL_MIRROR_TX,
  2071.                0);
  2072.     }
  2073.  
  2074.     /* now enable mirroring if necessary */
  2075.     if (priv->source_port >= AR8216_NUM_PORTS ||
  2076.         priv->monitor_port >= AR8216_NUM_PORTS ||
  2077.         priv->source_port == priv->monitor_port) {
  2078.         return;
  2079.     }
  2080.  
  2081.     ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
  2082.            AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
  2083.            (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
  2084.  
  2085.     if (priv->mirror_rx)
  2086.         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
  2087.                AR8216_PORT_CTRL_MIRROR_RX,
  2088.                AR8216_PORT_CTRL_MIRROR_RX);
  2089.  
  2090.     if (priv->mirror_tx)
  2091.         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
  2092.                AR8216_PORT_CTRL_MIRROR_TX,
  2093.                AR8216_PORT_CTRL_MIRROR_TX);
  2094. }
  2095.  
  2096. static void
  2097. ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
  2098. {
  2099.     if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
  2100.         ar8327_set_mirror_regs(priv);
  2101.     } else {
  2102.         ar8216_set_mirror_regs(priv);
  2103.     }
  2104. }
  2105.  
  2106. static int
  2107. ar8xxx_sw_hw_apply(struct switch_dev *dev)
  2108. {
  2109.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2110.     u8 portmask[AR8X16_MAX_PORTS];
  2111.     int i, j;
  2112.  
  2113.     mutex_lock(&priv->reg_mutex);
  2114.     /* flush all vlan translation unit entries */
  2115.     priv->chip->vtu_flush(priv);
  2116.  
  2117.     memset(portmask, 0, sizeof(portmask));
  2118.     if (!priv->init) {
  2119.         /* calculate the port destination masks and load vlans
  2120.          * into the vlan translation unit */
  2121.         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
  2122.             u8 vp = priv->vlan_table[j];
  2123.  
  2124.             if (!vp)
  2125.                 continue;
  2126.  
  2127.             for (i = 0; i < dev->ports; i++) {
  2128.                 u8 mask = BIT(i);
  2129.                 if (vp & mask)
  2130.                     portmask[i] |= vp & ~mask;
  2131.             }
  2132.             priv->chip->vtu_load_vlan(priv, j);
  2133.         }
  2134.     } else {
  2135.         /* vlan disabled:
  2136.          * isolate all ports, but connect them to the cpu port */
  2137.         for (i = 0; i < dev->ports; i++) {
  2138.             if (i == AR8216_PORT_CPU)
  2139.                 continue;
  2140.  
  2141.             portmask[i] = BIT(AR8216_PORT_CPU);
  2142.             portmask[AR8216_PORT_CPU] |= BIT(i);
  2143.         }
  2144.     }
  2145.  
  2146.     /* update the port destination mask registers and tag settings */
  2147.     for (i = 0; i < dev->ports; i++) {
  2148.         priv->chip->setup_port(priv, i, portmask[i]);
  2149.     }
  2150.  
  2151.     ar8xxx_set_mirror_regs(priv);
  2152.  
  2153.     mutex_unlock(&priv->reg_mutex);
  2154.     return 0;
  2155. }
  2156.  
  2157. static int
  2158. ar8xxx_sw_reset_switch(struct switch_dev *dev)
  2159. {
  2160.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2161.     int i;
  2162.  
  2163.     mutex_lock(&priv->reg_mutex);
  2164.     memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
  2165.         offsetof(struct ar8xxx_priv, vlan));
  2166.  
  2167.     for (i = 0; i < AR8X16_MAX_VLANS; i++)
  2168.         priv->vlan_id[i] = i;
  2169.  
  2170.     /* Configure all ports */
  2171.     for (i = 0; i < dev->ports; i++)
  2172.         priv->chip->init_port(priv, i);
  2173.  
  2174.     priv->mirror_rx = false;
  2175.     priv->mirror_tx = false;
  2176.     priv->source_port = 0;
  2177.     priv->monitor_port = 0;
  2178.  
  2179.     priv->chip->init_globals(priv);
  2180.  
  2181.     mutex_unlock(&priv->reg_mutex);
  2182.  
  2183.     return ar8xxx_sw_hw_apply(dev);
  2184. }
  2185.  
  2186. static int
  2187. ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
  2188.              const struct switch_attr *attr,
  2189.              struct switch_val *val)
  2190. {
  2191.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2192.     unsigned int len;
  2193.     int ret;
  2194.  
  2195.     if (!ar8xxx_has_mib_counters(priv))
  2196.         return -EOPNOTSUPP;
  2197.  
  2198.     mutex_lock(&priv->mib_lock);
  2199.  
  2200.     len = priv->dev.ports * priv->chip->num_mibs *
  2201.           sizeof(*priv->mib_stats);
  2202.     memset(priv->mib_stats, '\0', len);
  2203.     ret = ar8xxx_mib_flush(priv);
  2204.     if (ret)
  2205.         goto unlock;
  2206.  
  2207.     ret = 0;
  2208.  
  2209. unlock:
  2210.     mutex_unlock(&priv->mib_lock);
  2211.     return ret;
  2212. }
  2213.  
  2214. static int
  2215. ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
  2216.                    const struct switch_attr *attr,
  2217.                    struct switch_val *val)
  2218. {
  2219.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2220.  
  2221.     mutex_lock(&priv->reg_mutex);
  2222.     priv->mirror_rx = !!val->value.i;
  2223.     ar8xxx_set_mirror_regs(priv);
  2224.     mutex_unlock(&priv->reg_mutex);
  2225.  
  2226.     return 0;
  2227. }
  2228.  
  2229. static int
  2230. ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
  2231.                    const struct switch_attr *attr,
  2232.                    struct switch_val *val)
  2233. {
  2234.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2235.     val->value.i = priv->mirror_rx;
  2236.     return 0;
  2237. }
  2238.  
  2239. static int
  2240. ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
  2241.                    const struct switch_attr *attr,
  2242.                    struct switch_val *val)
  2243. {
  2244.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2245.  
  2246.     mutex_lock(&priv->reg_mutex);
  2247.     priv->mirror_tx = !!val->value.i;
  2248.     ar8xxx_set_mirror_regs(priv);
  2249.     mutex_unlock(&priv->reg_mutex);
  2250.  
  2251.     return 0;
  2252. }
  2253.  
  2254. static int
  2255. ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
  2256.                    const struct switch_attr *attr,
  2257.                    struct switch_val *val)
  2258. {
  2259.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2260.     val->value.i = priv->mirror_tx;
  2261.     return 0;
  2262. }
  2263.  
  2264. static int
  2265. ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
  2266.                   const struct switch_attr *attr,
  2267.                   struct switch_val *val)
  2268. {
  2269.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2270.  
  2271.     mutex_lock(&priv->reg_mutex);
  2272.     priv->monitor_port = val->value.i;
  2273.     ar8xxx_set_mirror_regs(priv);
  2274.     mutex_unlock(&priv->reg_mutex);
  2275.  
  2276.     return 0;
  2277. }
  2278.  
  2279. static int
  2280. ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
  2281.                   const struct switch_attr *attr,
  2282.                   struct switch_val *val)
  2283. {
  2284.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2285.     val->value.i = priv->monitor_port;
  2286.     return 0;
  2287. }
  2288.  
  2289. static int
  2290. ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
  2291.                  const struct switch_attr *attr,
  2292.                  struct switch_val *val)
  2293. {
  2294.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2295.  
  2296.     mutex_lock(&priv->reg_mutex);
  2297.     priv->source_port = val->value.i;
  2298.     ar8xxx_set_mirror_regs(priv);
  2299.     mutex_unlock(&priv->reg_mutex);
  2300.  
  2301.     return 0;
  2302. }
  2303.  
  2304. static int
  2305. ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
  2306.                  const struct switch_attr *attr,
  2307.                  struct switch_val *val)
  2308. {
  2309.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2310.     val->value.i = priv->source_port;
  2311.     return 0;
  2312. }
  2313.  
  2314. static int
  2315. ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
  2316.                  const struct switch_attr *attr,
  2317.                  struct switch_val *val)
  2318. {
  2319.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2320.     int port;
  2321.     int ret;
  2322.  
  2323.     if (!ar8xxx_has_mib_counters(priv))
  2324.         return -EOPNOTSUPP;
  2325.  
  2326.     port = val->port_vlan;
  2327.     if (port >= dev->ports)
  2328.         return -EINVAL;
  2329.  
  2330.     mutex_lock(&priv->mib_lock);
  2331.     ret = ar8xxx_mib_capture(priv);
  2332.     if (ret)
  2333.         goto unlock;
  2334.  
  2335.     ar8xxx_mib_fetch_port_stat(priv, port, true);
  2336.  
  2337.     ret = 0;
  2338.  
  2339. unlock:
  2340.     mutex_unlock(&priv->mib_lock);
  2341.     return ret;
  2342. }
  2343.  
  2344. static int
  2345. ar8xxx_sw_get_port_mib(struct switch_dev *dev,
  2346.                const struct switch_attr *attr,
  2347.                struct switch_val *val)
  2348. {
  2349.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2350.     const struct ar8xxx_chip *chip = priv->chip;
  2351.     u64 *mib_stats;
  2352.     int port;
  2353.     int ret;
  2354.     char *buf = priv->buf;
  2355.     int i, len = 0;
  2356.  
  2357.     if (!ar8xxx_has_mib_counters(priv))
  2358.         return -EOPNOTSUPP;
  2359.  
  2360.     port = val->port_vlan;
  2361.     if (port >= dev->ports)
  2362.         return -EINVAL;
  2363.  
  2364.     mutex_lock(&priv->mib_lock);
  2365.     ret = ar8xxx_mib_capture(priv);
  2366.     if (ret)
  2367.         goto unlock;
  2368.  
  2369.     ar8xxx_mib_fetch_port_stat(priv, port, false);
  2370.  
  2371.     len += snprintf(buf + len, sizeof(priv->buf) - len,
  2372.             "Port %d MIB counters\n",
  2373.             port);
  2374.  
  2375.     mib_stats = &priv->mib_stats[port * chip->num_mibs];
  2376.     for (i = 0; i < chip->num_mibs; i++)
  2377.         len += snprintf(buf + len, sizeof(priv->buf) - len,
  2378.                 "%-12s: %llu\n",
  2379.                 chip->mib_decs[i].name,
  2380.                 mib_stats[i]);
  2381.  
  2382.     val->value.s = buf;
  2383.     val->len = len;
  2384.  
  2385.     ret = 0;
  2386.  
  2387. unlock:
  2388.     mutex_unlock(&priv->mib_lock);
  2389.     return ret;
  2390. }
  2391.  
  2392. static struct switch_attr ar8xxx_sw_attr_globals[] = {
  2393.     {
  2394.         .type = SWITCH_TYPE_INT,
  2395.         .name = "enable_vlan",
  2396.         .description = "Enable VLAN mode",
  2397.         .set = ar8xxx_sw_set_vlan,
  2398.         .get = ar8xxx_sw_get_vlan,
  2399.         .max = 1
  2400.     },
  2401.     {
  2402.         .type = SWITCH_TYPE_NOVAL,
  2403.         .name = "reset_mibs",
  2404.         .description = "Reset all MIB counters",
  2405.         .set = ar8xxx_sw_set_reset_mibs,
  2406.     },
  2407.     {
  2408.         .type = SWITCH_TYPE_INT,
  2409.         .name = "enable_mirror_rx",
  2410.         .description = "Enable mirroring of RX packets",
  2411.         .set = ar8xxx_sw_set_mirror_rx_enable,
  2412.         .get = ar8xxx_sw_get_mirror_rx_enable,
  2413.         .max = 1
  2414.     },
  2415.     {
  2416.         .type = SWITCH_TYPE_INT,
  2417.         .name = "enable_mirror_tx",
  2418.         .description = "Enable mirroring of TX packets",
  2419.         .set = ar8xxx_sw_set_mirror_tx_enable,
  2420.         .get = ar8xxx_sw_get_mirror_tx_enable,
  2421.         .max = 1
  2422.     },
  2423.     {
  2424.         .type = SWITCH_TYPE_INT,
  2425.         .name = "mirror_monitor_port",
  2426.         .description = "Mirror monitor port",
  2427.         .set = ar8xxx_sw_set_mirror_monitor_port,
  2428.         .get = ar8xxx_sw_get_mirror_monitor_port,
  2429.         .max = AR8216_NUM_PORTS - 1
  2430.     },
  2431.     {
  2432.         .type = SWITCH_TYPE_INT,
  2433.         .name = "mirror_source_port",
  2434.         .description = "Mirror source port",
  2435.         .set = ar8xxx_sw_set_mirror_source_port,
  2436.         .get = ar8xxx_sw_get_mirror_source_port,
  2437.         .max = AR8216_NUM_PORTS - 1
  2438.     },
  2439. };
  2440.  
  2441. static struct switch_attr ar8327_sw_attr_globals[] = {
  2442.     {
  2443.         .type = SWITCH_TYPE_INT,
  2444.         .name = "enable_vlan",
  2445.         .description = "Enable VLAN mode",
  2446.         .set = ar8xxx_sw_set_vlan,
  2447.         .get = ar8xxx_sw_get_vlan,
  2448.         .max = 1
  2449.     },
  2450.     {
  2451.         .type = SWITCH_TYPE_NOVAL,
  2452.         .name = "reset_mibs",
  2453.         .description = "Reset all MIB counters",
  2454.         .set = ar8xxx_sw_set_reset_mibs,
  2455.     },
  2456.     {
  2457.         .type = SWITCH_TYPE_INT,
  2458.         .name = "enable_mirror_rx",
  2459.         .description = "Enable mirroring of RX packets",
  2460.         .set = ar8xxx_sw_set_mirror_rx_enable,
  2461.         .get = ar8xxx_sw_get_mirror_rx_enable,
  2462.         .max = 1
  2463.     },
  2464.     {
  2465.         .type = SWITCH_TYPE_INT,
  2466.         .name = "enable_mirror_tx",
  2467.         .description = "Enable mirroring of TX packets",
  2468.         .set = ar8xxx_sw_set_mirror_tx_enable,
  2469.         .get = ar8xxx_sw_get_mirror_tx_enable,
  2470.         .max = 1
  2471.     },
  2472.     {
  2473.         .type = SWITCH_TYPE_INT,
  2474.         .name = "mirror_monitor_port",
  2475.         .description = "Mirror monitor port",
  2476.         .set = ar8xxx_sw_set_mirror_monitor_port,
  2477.         .get = ar8xxx_sw_get_mirror_monitor_port,
  2478.         .max = AR8327_NUM_PORTS - 1
  2479.     },
  2480.     {
  2481.         .type = SWITCH_TYPE_INT,
  2482.         .name = "mirror_source_port",
  2483.         .description = "Mirror source port",
  2484.         .set = ar8xxx_sw_set_mirror_source_port,
  2485.         .get = ar8xxx_sw_get_mirror_source_port,
  2486.         .max = AR8327_NUM_PORTS - 1
  2487.     },
  2488. };
  2489.  
  2490. static struct switch_attr ar8xxx_sw_attr_port[] = {
  2491.     {
  2492.         .type = SWITCH_TYPE_NOVAL,
  2493.         .name = "reset_mib",
  2494.         .description = "Reset single port MIB counters",
  2495.         .set = ar8xxx_sw_set_port_reset_mib,
  2496.     },
  2497.     {
  2498.         .type = SWITCH_TYPE_STRING,
  2499.         .name = "mib",
  2500.         .description = "Get port's MIB counters",
  2501.         .set = NULL,
  2502.         .get = ar8xxx_sw_get_port_mib,
  2503.     },
  2504. };
  2505.  
  2506. static struct switch_attr ar8xxx_sw_attr_vlan[] = {
  2507.     {
  2508.         .type = SWITCH_TYPE_INT,
  2509.         .name = "vid",
  2510.         .description = "VLAN ID (0-4094)",
  2511.         .set = ar8xxx_sw_set_vid,
  2512.         .get = ar8xxx_sw_get_vid,
  2513.         .max = 4094,
  2514.     },
  2515. };
  2516.  
  2517. static const struct switch_dev_ops ar8xxx_sw_ops = {
  2518.     .attr_global = {
  2519.         .attr = ar8xxx_sw_attr_globals,
  2520.         .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
  2521.     },
  2522.     .attr_port = {
  2523.         .attr = ar8xxx_sw_attr_port,
  2524.         .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
  2525.     },
  2526.     .attr_vlan = {
  2527.         .attr = ar8xxx_sw_attr_vlan,
  2528.         .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
  2529.     },
  2530.     .get_port_pvid = ar8xxx_sw_get_pvid,
  2531.     .set_port_pvid = ar8xxx_sw_set_pvid,
  2532.     .get_vlan_ports = ar8216_sw_get_ports,
  2533.     .set_vlan_ports = ar8216_sw_set_ports,
  2534.     .apply_config = ar8xxx_sw_hw_apply,
  2535.     .reset_switch = ar8xxx_sw_reset_switch,
  2536.     .get_port_link = ar8xxx_sw_get_port_link,
  2537. };
  2538.  
  2539. static const struct switch_dev_ops ar8327_sw_ops = {
  2540.     .attr_global = {
  2541.         .attr = ar8327_sw_attr_globals,
  2542.         .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
  2543.     },
  2544.     .attr_port = {
  2545.         .attr = ar8xxx_sw_attr_port,
  2546.         .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
  2547.     },
  2548.     .attr_vlan = {
  2549.         .attr = ar8xxx_sw_attr_vlan,
  2550.         .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
  2551.     },
  2552.     .get_port_pvid = ar8xxx_sw_get_pvid,
  2553.     .set_port_pvid = ar8xxx_sw_set_pvid,
  2554.     .get_vlan_ports = ar8327_sw_get_ports,
  2555.     .set_vlan_ports = ar8327_sw_set_ports,
  2556.     .apply_config = ar8xxx_sw_hw_apply,
  2557.     .reset_switch = ar8xxx_sw_reset_switch,
  2558.     .get_port_link = ar8xxx_sw_get_port_link,
  2559. };
  2560.  
  2561. static int
  2562. ar8xxx_id_chip(struct ar8xxx_priv *priv)
  2563. {
  2564.     u32 val;
  2565.     u16 id;
  2566.     int i;
  2567.  
  2568.     val = priv->read(priv, AR8216_REG_CTRL);
  2569.     if (val == ~0)
  2570.         return -ENODEV;
  2571.  
  2572.     id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
  2573.     for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
  2574.         u16 t;
  2575.  
  2576.         val = priv->read(priv, AR8216_REG_CTRL);
  2577.         if (val == ~0)
  2578.             return -ENODEV;
  2579.  
  2580.         t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
  2581.         if (t != id)
  2582.             return -ENODEV;
  2583.     }
  2584.  
  2585.     priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
  2586.     priv->chip_rev = (id & AR8216_CTRL_REVISION);
  2587.  
  2588.     switch (priv->chip_ver) {
  2589.     case AR8XXX_VER_AR8216:
  2590.         priv->chip = &ar8216_chip;
  2591.         break;
  2592.     case AR8XXX_VER_AR8236:
  2593.         priv->chip = &ar8236_chip;
  2594.         break;
  2595.     case AR8XXX_VER_AR8316:
  2596.         priv->chip = &ar8316_chip;
  2597.         break;
  2598.     case AR8XXX_VER_AR8327:
  2599.         priv->mii_lo_first = true;
  2600.         priv->chip = &ar8327_chip;
  2601.         break;
  2602.     case AR8XXX_VER_AR8337:
  2603.         priv->mii_lo_first = true;
  2604.         priv->chip = &ar8327_chip;
  2605.         break;
  2606.     default:
  2607.         pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
  2608.                priv->chip_ver, priv->chip_rev);
  2609.  
  2610.         return -ENODEV;
  2611.     }
  2612.  
  2613.     return 0;
  2614. }
  2615.  
  2616. static void
  2617. ar8xxx_mib_work_func(struct work_struct *work)
  2618. {
  2619.     struct ar8xxx_priv *priv;
  2620.     int err;
  2621.  
  2622.     priv = container_of(work, struct ar8xxx_priv, mib_work.work);
  2623.  
  2624.     mutex_lock(&priv->mib_lock);
  2625.  
  2626.     err = ar8xxx_mib_capture(priv);
  2627.     if (err)
  2628.         goto next_port;
  2629.  
  2630.     ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
  2631.  
  2632. next_port:
  2633.     priv->mib_next_port++;
  2634.     if (priv->mib_next_port >= priv->dev.ports)
  2635.         priv->mib_next_port = 0;
  2636.  
  2637.     mutex_unlock(&priv->mib_lock);
  2638.     schedule_delayed_work(&priv->mib_work,
  2639.                   msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
  2640. }
  2641.  
  2642. static int
  2643. ar8xxx_mib_init(struct ar8xxx_priv *priv)
  2644. {
  2645.     unsigned int len;
  2646.  
  2647.     if (!ar8xxx_has_mib_counters(priv))
  2648.         return 0;
  2649.  
  2650.     BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
  2651.  
  2652.     len = priv->dev.ports * priv->chip->num_mibs *
  2653.           sizeof(*priv->mib_stats);
  2654.     priv->mib_stats = kzalloc(len, GFP_KERNEL);
  2655.  
  2656.     if (!priv->mib_stats)
  2657.         return -ENOMEM;
  2658.  
  2659.     return 0;
  2660. }
  2661.  
  2662. static void
  2663. ar8xxx_mib_start(struct ar8xxx_priv *priv)
  2664. {
  2665.     if (!ar8xxx_has_mib_counters(priv))
  2666.         return;
  2667.  
  2668.     schedule_delayed_work(&priv->mib_work,
  2669.                   msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
  2670. }
  2671.  
  2672. static void
  2673. ar8xxx_mib_stop(struct ar8xxx_priv *priv)
  2674. {
  2675.     if (!ar8xxx_has_mib_counters(priv))
  2676.         return;
  2677.  
  2678.     cancel_delayed_work(&priv->mib_work);
  2679. }
  2680.  
  2681. static struct ar8xxx_priv *
  2682. ar8xxx_create(void)
  2683. {
  2684.     struct ar8xxx_priv *priv;
  2685.  
  2686.     priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
  2687.     if (priv == NULL)
  2688.         return NULL;
  2689.  
  2690.     mutex_init(&priv->reg_mutex);
  2691.     mutex_init(&priv->mib_lock);
  2692.     INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
  2693.  
  2694.     return priv;
  2695. }
  2696.  
  2697. static void
  2698. ar8xxx_free(struct ar8xxx_priv *priv)
  2699. {
  2700.     if (priv->chip && priv->chip->cleanup)
  2701.         priv->chip->cleanup(priv);
  2702.  
  2703.     kfree(priv->mib_stats);
  2704.     kfree(priv);
  2705. }
  2706.  
  2707. static struct ar8xxx_priv *
  2708. ar8xxx_create_mii(struct mii_bus *bus)
  2709. {
  2710.     struct ar8xxx_priv *priv;
  2711.  
  2712.     priv = ar8xxx_create();
  2713.     if (priv) {
  2714.         priv->mii_bus = bus;
  2715.         priv->read = ar8xxx_mii_read;
  2716.         priv->write = ar8xxx_mii_write;
  2717.         priv->rmw = ar8xxx_mii_rmw;
  2718.     }
  2719.  
  2720.     return priv;
  2721. }
  2722.  
  2723. static int
  2724. ar8xxx_probe_switch(struct ar8xxx_priv *priv)
  2725. {
  2726.     struct switch_dev *swdev;
  2727.     int ret;
  2728.  
  2729.     ret = ar8xxx_id_chip(priv);
  2730.     if (ret)
  2731.         return ret;
  2732.  
  2733.     swdev = &priv->dev;
  2734.     swdev->cpu_port = AR8216_PORT_CPU;
  2735.     swdev->ops = &ar8xxx_sw_ops;
  2736.  
  2737.     if (chip_is_ar8316(priv)) {
  2738.         swdev->name = "Atheros AR8316";
  2739.         swdev->vlans = AR8X16_MAX_VLANS;
  2740.         swdev->ports = AR8216_NUM_PORTS;
  2741.     } else if (chip_is_ar8236(priv)) {
  2742.         swdev->name = "Atheros AR8236";
  2743.         swdev->vlans = AR8216_NUM_VLANS;
  2744.         swdev->ports = AR8216_NUM_PORTS;
  2745.     } else if (chip_is_ar8327(priv)) {
  2746.         swdev->name = "Atheros AR8327";
  2747.         swdev->vlans = AR8X16_MAX_VLANS;
  2748.         swdev->ports = AR8327_NUM_PORTS;
  2749.         swdev->ops = &ar8327_sw_ops;
  2750.     } else if (chip_is_ar8337(priv)) {
  2751.         swdev->name = "Atheros AR8337";
  2752.         swdev->vlans = AR8X16_MAX_VLANS;
  2753.         swdev->ports = AR8327_NUM_PORTS;
  2754.         swdev->ops = &ar8327_sw_ops;
  2755.     } else {
  2756.         swdev->name = "Atheros AR8216";
  2757.         swdev->vlans = AR8216_NUM_VLANS;
  2758.         swdev->ports = AR8216_NUM_PORTS;
  2759.     }
  2760.  
  2761.     ret = ar8xxx_mib_init(priv);
  2762.     if (ret)
  2763.         return ret;
  2764.  
  2765.     return 0;
  2766. }
  2767.  
  2768. static int
  2769. ar8xxx_start(struct ar8xxx_priv *priv)
  2770. {
  2771.     int ret;
  2772.  
  2773.     priv->init = true;
  2774.  
  2775.     ret = priv->chip->hw_init(priv);
  2776.     if (ret)
  2777.         return ret;
  2778.  
  2779.     ret = ar8xxx_sw_reset_switch(&priv->dev);
  2780.     if (ret)
  2781.         return ret;
  2782.  
  2783.     priv->init = false;
  2784.  
  2785.     ar8xxx_mib_start(priv);
  2786.  
  2787.     return 0;
  2788. }
  2789.  
  2790. static int
  2791. ar8xxx_phy_config_init(struct phy_device *phydev)
  2792. {
  2793.     struct ar8xxx_priv *priv = phydev->priv;
  2794.     struct net_device *dev = phydev->attached_dev;
  2795.     int ret;
  2796.  
  2797.     if (WARN_ON(!priv))
  2798.         return -ENODEV;
  2799.  
  2800.     if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
  2801.         return 0;
  2802.  
  2803.     priv->phy = phydev;
  2804.  
  2805.     if (phydev->addr != 0) {
  2806.         if (chip_is_ar8316(priv)) {
  2807.             /* switch device has been initialized, reinit */
  2808.             priv->dev.ports = (AR8216_NUM_PORTS - 1);
  2809.             priv->initialized = false;
  2810.             priv->port4_phy = true;
  2811.             ar8316_hw_init(priv);
  2812.             return 0;
  2813.         }
  2814.  
  2815.         return 0;
  2816.     }
  2817.  
  2818.     ret = ar8xxx_start(priv);
  2819.     if (ret)
  2820.         return ret;
  2821.  
  2822.     /* VID fixup only needed on ar8216 */
  2823.     if (chip_is_ar8216(priv)) {
  2824.         dev->phy_ptr = priv;
  2825.         dev->priv_flags |= IFF_NO_IP_ALIGN;
  2826.         dev->eth_mangle_rx = ar8216_mangle_rx;
  2827.         dev->eth_mangle_tx = ar8216_mangle_tx;
  2828.     }
  2829.  
  2830.     return 0;
  2831. }
  2832.  
  2833. static int
  2834. ar8xxx_phy_read_status(struct phy_device *phydev)
  2835. {
  2836.     struct ar8xxx_priv *priv = phydev->priv;
  2837.     struct switch_port_link link;
  2838.     int ret;
  2839.  
  2840.     if (phydev->addr != 0)
  2841.         return genphy_read_status(phydev);
  2842.  
  2843.     ar8216_read_port_link(priv, phydev->addr, &link);
  2844.     phydev->link = !!link.link;
  2845.     if (!phydev->link)
  2846.         return 0;
  2847.  
  2848.     switch (link.speed) {
  2849.     case SWITCH_PORT_SPEED_10:
  2850.         phydev->speed = SPEED_10;
  2851.         break;
  2852.     case SWITCH_PORT_SPEED_100:
  2853.         phydev->speed = SPEED_100;
  2854.         break;
  2855.     case SWITCH_PORT_SPEED_1000:
  2856.         phydev->speed = SPEED_1000;
  2857.         break;
  2858.     default:
  2859.         phydev->speed = 0;
  2860.     }
  2861.     phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
  2862.  
  2863.     /* flush the address translation unit */
  2864.     mutex_lock(&priv->reg_mutex);
  2865.     ret = priv->chip->atu_flush(priv);
  2866.     mutex_unlock(&priv->reg_mutex);
  2867.  
  2868.     phydev->state = PHY_RUNNING;
  2869.     netif_carrier_on(phydev->attached_dev);
  2870.     phydev->adjust_link(phydev->attached_dev);
  2871.  
  2872.     return ret;
  2873. }
  2874.  
  2875. static int
  2876. ar8xxx_phy_config_aneg(struct phy_device *phydev)
  2877. {
  2878.     if (phydev->addr == 0)
  2879.         return 0;
  2880.  
  2881.     return genphy_config_aneg(phydev);
  2882. }
  2883.  
  2884. static const u32 ar8xxx_phy_ids[] = {
  2885.     0x004dd033,
  2886.     0x004dd034, /* AR8327 */
  2887.     0x004dd036, /* AR8337 */
  2888.     0x004dd041,
  2889.     0x004dd042,
  2890. };
  2891.  
  2892. static bool
  2893. ar8xxx_phy_match(u32 phy_id)
  2894. {
  2895.     int i;
  2896.  
  2897.     for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
  2898.         if (phy_id == ar8xxx_phy_ids[i])
  2899.             return true;
  2900.  
  2901.     return false;
  2902. }
  2903.  
  2904. static bool
  2905. ar8xxx_is_possible(struct mii_bus *bus)
  2906. {
  2907.     unsigned i;
  2908.  
  2909.     for (i = 0; i < 4; i++) {
  2910.         u32 phy_id;
  2911.  
  2912.         phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
  2913.         phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
  2914.         if (!ar8xxx_phy_match(phy_id)) {
  2915.             pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
  2916.                  dev_name(&bus->dev), i, phy_id);
  2917.             return false;
  2918.         }
  2919.     }
  2920.  
  2921.     return true;
  2922. }
  2923.  
  2924. static int
  2925. ar8xxx_phy_probe(struct phy_device *phydev)
  2926. {
  2927.     struct ar8xxx_priv *priv;
  2928.     struct switch_dev *swdev;
  2929.     int ret;
  2930.  
  2931.     /* skip PHYs at unused adresses */
  2932.     if (phydev->addr != 0 && phydev->addr != 4)
  2933.         return -ENODEV;
  2934.  
  2935.     if (!ar8xxx_is_possible(phydev->bus))
  2936.         return -ENODEV;
  2937.  
  2938.     mutex_lock(&ar8xxx_dev_list_lock);
  2939.     list_for_each_entry(priv, &ar8xxx_dev_list, list)
  2940.         if (priv->mii_bus == phydev->bus)
  2941.             goto found;
  2942.  
  2943.     priv = ar8xxx_create_mii(phydev->bus);
  2944.     if (priv == NULL) {
  2945.         ret = -ENOMEM;
  2946.         goto unlock;
  2947.     }
  2948.  
  2949.     ret = ar8xxx_probe_switch(priv);
  2950.     if (ret)
  2951.         goto free_priv;
  2952.  
  2953.     swdev = &priv->dev;
  2954.     swdev->alias = dev_name(&priv->mii_bus->dev);
  2955.     ret = register_switch(swdev, NULL);
  2956.     if (ret)
  2957.         goto free_priv;
  2958.  
  2959.     pr_info("%s: %s rev. %u switch registered on %s\n",
  2960.         swdev->devname, swdev->name, priv->chip_rev,
  2961.         dev_name(&priv->mii_bus->dev));
  2962.  
  2963. found:
  2964.     priv->use_count++;
  2965.  
  2966.     if (phydev->addr == 0) {
  2967.         if (ar8xxx_has_gige(priv)) {
  2968.             phydev->supported = SUPPORTED_1000baseT_Full;
  2969.             phydev->advertising = ADVERTISED_1000baseT_Full;
  2970.         } else {
  2971.             phydev->supported = SUPPORTED_100baseT_Full;
  2972.             phydev->advertising = ADVERTISED_100baseT_Full;
  2973.         }
  2974.  
  2975.         if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
  2976.             priv->phy = phydev;
  2977.  
  2978.             ret = ar8xxx_start(priv);
  2979.             if (ret)
  2980.                 goto err_unregister_switch;
  2981.         }
  2982.     } else {
  2983.         if (ar8xxx_has_gige(priv)) {
  2984.             phydev->supported |= SUPPORTED_1000baseT_Full;
  2985.             phydev->advertising |= ADVERTISED_1000baseT_Full;
  2986.         }
  2987.     }
  2988.  
  2989.     phydev->priv = priv;
  2990.  
  2991.     list_add(&priv->list, &ar8xxx_dev_list);
  2992.  
  2993.     mutex_unlock(&ar8xxx_dev_list_lock);
  2994.  
  2995.     return 0;
  2996.  
  2997. err_unregister_switch:
  2998.     if (--priv->use_count)
  2999.         goto unlock;
  3000.  
  3001.     unregister_switch(&priv->dev);
  3002.  
  3003. free_priv:
  3004.     ar8xxx_free(priv);
  3005. unlock:
  3006.     mutex_unlock(&ar8xxx_dev_list_lock);
  3007.     return ret;
  3008. }
  3009.  
  3010. static void
  3011. ar8xxx_phy_detach(struct phy_device *phydev)
  3012. {
  3013.     struct net_device *dev = phydev->attached_dev;
  3014.  
  3015.     if (!dev)
  3016.         return;
  3017.  
  3018.     dev->phy_ptr = NULL;
  3019.     dev->priv_flags &= ~IFF_NO_IP_ALIGN;
  3020.     dev->eth_mangle_rx = NULL;
  3021.     dev->eth_mangle_tx = NULL;
  3022. }
  3023.  
  3024. static void
  3025. ar8xxx_phy_remove(struct phy_device *phydev)
  3026. {
  3027.     struct ar8xxx_priv *priv = phydev->priv;
  3028.  
  3029.     if (WARN_ON(!priv))
  3030.         return;
  3031.  
  3032.     phydev->priv = NULL;
  3033.     if (--priv->use_count > 0)
  3034.         return;
  3035.  
  3036.     mutex_lock(&ar8xxx_dev_list_lock);
  3037.     list_del(&priv->list);
  3038.     mutex_unlock(&ar8xxx_dev_list_lock);
  3039.  
  3040.     unregister_switch(&priv->dev);
  3041.     ar8xxx_mib_stop(priv);
  3042.     ar8xxx_free(priv);
  3043. }
  3044.  
  3045. static struct phy_driver ar8xxx_phy_driver = {
  3046.     .phy_id     = 0x004d0000,
  3047.     .name       = "Atheros AR8216/AR8236/AR8316",
  3048.     .phy_id_mask    = 0xffff0000,
  3049.     .features   = PHY_BASIC_FEATURES,
  3050.     .probe      = ar8xxx_phy_probe,
  3051.     .remove     = ar8xxx_phy_remove,
  3052.     .detach     = ar8xxx_phy_detach,
  3053.     .config_init    = ar8xxx_phy_config_init,
  3054.     .config_aneg    = ar8xxx_phy_config_aneg,
  3055.     .read_status    = ar8xxx_phy_read_status,
  3056.     .driver     = { .owner = THIS_MODULE },
  3057. };
  3058.  
  3059. int __init
  3060. ar8xxx_init(void)
  3061. {
  3062.     return phy_driver_register(&ar8xxx_phy_driver);
  3063. }
  3064.  
  3065. void __exit
  3066. ar8xxx_exit(void)
  3067. {
  3068.     phy_driver_unregister(&ar8xxx_phy_driver);
  3069. }
  3070.  
  3071. module_init(ar8xxx_init);
  3072. module_exit(ar8xxx_exit);
  3073. MODULE_LICENSE("GPL");
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