library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.core_pack.all;

entity regfile is

	port (
		clk, reset       : in  std_logic;
		stall            : in  std_logic;
		rdaddr1, rdaddr2 : in  std_logic_vector(REG_BITS-1 downto 0);
		rddata1, rddata2 : out std_logic_vector(DATA_WIDTH-1 downto 0);
		wraddr			 : in  std_logic_vector(REG_BITS-1 downto 0);
		wrdata			 : in  std_logic_vector(DATA_WIDTH-1 downto 0);
		regwrite         : in  std_logic);

end regfile;

architecture rtl of regfile is
	subtype REG_ENTRY_TYPE is std_logic_vector (DATA_WIDTH - 1 downto 0);
	type REG_TYPE is array (0 to (REG_COUNT) - 1) of REG_ENTRY_TYPE;
	signal reg : REG_TYPE := (others => x"00000000");
	signal rdaddr1_sig, rdaddr2_sig : std_logic_vector(REG_BITS-1 downto 0);

begin  -- rtl

process(rdaddr1_sig, rdaddr2_sig, wraddr,regwrite,wrdata,reg)
begin
	if stall = '0' then
		if rdaddr1_sig = wraddr and regwrite = '1' then
			rddata1 <= wrdata;
			rddata2 <= reg(to_integer(unsigned(rdaddr2_sig)));
		elsif rdaddr2_sig = wraddr and regwrite = '1' then
			rddata1 <= reg(to_integer(unsigned(rdaddr1_sig)));
			rddata2 <= wrdata;
		elsif rdaddr1_sig = wraddr and rdaddr2_sig = wraddr and regwrite = '1' then
			rddata1 <= wrdata;
			rddata2 <= wrdata;
		else
			rddata1 <= reg(to_integer(unsigned(rdaddr1_sig)));
			rddata2 <= reg(to_integer(unsigned(rdaddr2_sig)));
		end if;

		if rdaddr1 = "00000" then
			rddata1 <= (others => '0');
		end if;
		if rdaddr2 = "00000" then
			rddata2 <= (others => '0');
		end if;
	end if;

end process;

	process(clk, reset)
  begin
    if reset = '0' then
		reg <= (others => x"00000000");
		--rddata1 <= (others => '0');
		--rddata2 <= (others => '0');
    elsif rising_edge(clk) then
	rdaddr1_sig <= rdaddr1;
	rdaddr2_sig <=rdaddr2;
		if regwrite = '1' then
			if wraddr /= "00000" and stall /= '1' then
				reg(to_integer(unsigned(wraddr))) <= wrdata;
			end if;
		end if;
    end if;

  end process;
end rtl;