ALUx8

def mux21x
  port in i0
  port in i1
  port in s
  port in ns
  port out z

  net nsi0
  net si1

  inst n1 nand ns i0 nsi0
  inst n2 nand s i1 si1
  inst n3 nand nsi0 si1 z
enddef

def mux41x
  port in i0
  port in i1
  port in i2
  port in i3
  port in s<1:0>
  port in ns1
  port in ns0
  port out z

  net i01
  net i23

  inst m0 mux21x i0 i1 s<0> ns0 i01
  inst m1 mux21x i2 i3 s<0> ns0 i23
  inst m2 mux21x i01 i23 s<1> ns1 z
enddef

def mux41x8
  port in i0<7:0>
  port in i1<7:0>
  port in i2<7:0>
  port in i3<7:0>
  port in s<1:0>
  port out z<7:0>

  net ns0
  net ns1

  inst n0 nand s<0> s<0> ns0
  inst n1 nand s<1> s<1> ns1

  inst m7 mux41x i0<7> i1<7> i2<7> i3<7> s<1:0> ns1 ns0 z<7>
  inst m6 mux41x i0<6> i1<6> i2<6> i3<6> s<1:0> ns1 ns0 z<6>
  inst m5 mux41x i0<5> i1<5> i2<5> i3<5> s<1:0> ns1 ns0 z<5>
  inst m4 mux41x i0<4> i1<4> i2<4> i3<4> s<1:0> ns1 ns0 z<4>
  inst m3 mux41x i0<3> i1<3> i2<3> i3<3> s<1:0> ns1 ns0 z<3>
  inst m2 mux41x i0<2> i1<2> i2<2> i3<2> s<1:0> ns1 ns0 z<2>
  inst m1 mux41x i0<1> i1<1> i2<1> i3<1> s<1:0> ns1 ns0 z<1>
  inst m0 mux41x i0<0> i1<0> i2<0> i3<0> s<1:0> ns1 ns0 z<0>
enddef


def alux1
  port in a
  port in b
  port in ci
  port out s
  port out co
  port out or
  port out and
  port out nota

  net nc1
  net nc2
  net a2
  net b2
  net s1
  net c3
  net s12
  net notb

  inst n1 nand a b nc1
  inst n2 nand a nc1 a2
  inst n3 nand b nc1 b2
  inst n4 nand a2 b2 s1
  inst n5 nand ci s1 nc2
  inst n6 nand ci nc2 c3
  inst n7 nand s1 nc2 s12
  inst n8 nand c3 s12 s
  inst n9 nand nc1 nc2 co
  inst na nand a a nota
  inst nb nand b b notb
  inst no nand nota notb or
  inst nn nand nc1 nc1 and
enddef

def alux1nci  #No carry in
  port in a
  port in b
#  port in ci   Always False
  port out s
#  port out co  Always = "And" output
  port out or
  port out and
  port out nota

  net nc1
  net nc2
  net a2
  net b2
  net s1
  net c3
  net s12
  net notb

  inst n1 nand a b nc1
  inst n2 nand a nc1 a2
  inst n3 nand b nc1 b2
  inst n4 nand a2 b2 s
#  inst n5 nand ci s1 nc2
#  inst n6 nand ci nc2 c3
#  inst n7 nand s1 nc2 s12
#  inst n8 nand c3 s12 s
#  inst n9 nand nc1 nc2 co
  inst na nand a a nota
  inst nb nand b b notb
  inst no nand nota notb or
  inst nn nand nc1 nc1 and
enddef

def alux1nco  #No carry out.
  port in a
  port in b
  port in ci
  port out s
#  port out co
  port out or
  port out and
  port out nota

  net nc1
  net nc2
  net a2
  net b2
  net s1
  net c3
  net s12
  net notb

  inst n1 nand a b nc1
  inst n2 nand a nc1 a2
  inst n3 nand b nc1 b2
  inst n4 nand a2 b2 s1
  inst n5 nand ci s1 nc2
  inst n6 nand ci nc2 c3
  inst n7 nand s1 nc2 s12
  inst n8 nand c3 s12 s
#  inst n9 nand nc1 nc2 co
  inst na nand a a nota
  inst nb nand b b notb
  inst no nand nota notb or
  inst nn nand nc1 nc1 and
enddef

def alux8
  port in a<7:0>
  port in b<7:0>
  port in op<1:0>
  port out z<7:0>

 # net c1    =and<0>
  net c2
  net c3
  net c4
  net c5
  net c6
  net c7
  net or<7:0>
  net and<7:0>
  net not<7:0>
  net sum<7:0>
  net cout

  inst a0 alux1nci a<0> b<0>        sum<0>    or<0> and<0> not<0>
  inst a1 alux1    a<1> b<1> and<0> sum<1> c2 or<1> and<1> not<1>
  inst a2 alux1    a<2> b<2> c2     sum<2> c3 or<2> and<2> not<2>
  inst a3 alux1    a<3> b<3> c3     sum<3> c4 or<3> and<3> not<3>
  inst a4 alux1    a<4> b<4> c4     sum<4> c5 or<4> and<4> not<4>
  inst a5 alux1    a<5> b<5> c5     sum<5> c6 or<5> and<5> not<5>
  inst a6 alux1    a<6> b<6> c6     sum<6> c7 or<6> and<6> not<6>
  inst a7 alux1nco a<7> b<7> c7     sum<7>    or<7> and<7> not<7>

  inst m1 mux41x8 sum<7:0> and<7:0> or<7:0> not<7:0> op<1:0> z<7:0>
enddef