------------------------------------------------------------------
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 library work;
 ------------------------------------------------------------------
 ENTITY rom IS
PORT (clk: IN STD_LOGIC;
address: IN INTEGER RANGE 0 to 2**15;
data_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END rom;
------------------------------------------------------------------
ARCHITECTURE rom OF rom IS
SIGNAL reg_address: INTEGER RANGE 0 to 2**15;
TYPE memory IS ARRAY (0 TO 15) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
 CONSTANT myrom: memory := (
0=>	 "00000000", -- 0
1=>    "00000000", -- 1
2=>    "00010000", -- 2    *
3=>    "00111000", -- 3   ***
4=>    "01101100", -- 4  ** **
5=>    "11000110", -- 5 **   **
6=>    "11000110", -- 6 **   **
7=>    "11111110", -- 7 *******
8=>    "11000110", -- 8 **   **
9=>    "11000110", -- 9 **   **
10=>   "11000110", -- a **   **
11=>   "11000110", -- b **   **
12=>   "00000000", -- c
13=>   "00000000", -- d
14=>   "00000000", -- e
15=>   "00000000", -- f
 OTHERS => "00000000");
 BEGIN
 --Register the address:----------
 PROCESS (clk)
 BEGIN IF (clk'EVENT AND clk='1') THEN
 reg_address <= address;
 END IF;
 END PROCESS;
--Get unregistered output:-------
 data_out <= myrom(reg_address);
 END rom;