from migen import *
from migen.build.platforms import papilio_pro

from misoc.cores.uart.core import RS232PHY
import wishbonebridge

from misoc.interconnect import wishbone, csr_bus

platform = papilio_pro.Platform()


class MyWishbone(Module):
    def __init__(self):
        self.wb = wb = wishbone.Interface()

        counter1 = Signal(32, reset=0xdeadbeef)
        counter2 = Signal(32, reset=0x12345678)

        self.sync += [
            If(wb.adr[0],
               wb.dat_r.eq(counter1)
            ).Else(
                wb.dat_r.eq(counter2)
            ),

            wb.ack.eq(0),
            If(wb.cyc & wb.stb & ~wb.ack,
               wb.ack.eq(1),
               If(wb.we,
                  If(wb.adr[0],
                     counter1.eq(wb.dat_w)
                  ).Else(counter2.eq(wb.dat_w))
               )
            )
            ]

class WBTest(Module):
    def __init__(self):
        counter = Signal(32)

        self.submodules.phy = RS232PHY(platform.request("serial"), 32000000, 115200)
        self.submodules.bridge = wishbonebridge.WishboneStreamingBridge(self.phy, 32000000)

        self.submodules.mywb = MyWishbone()

        wishbone.InterconnectPointToPoint(self.bridge.wishbone, self.mywb.wb)

if __name__ == "__main__":

    top = WBTest()
    platform.build(top, build_dir="wbtest")