gpmc_sync_nor_read_write

/*
Test file for talking to external memory using GPMC pins in GPMC mode.
*/
#include <stdio.h>
#include <fcntl.h>
#include <sys/mman.h>
#include "hw_gpmc.h" // SYS-BIOS
#include "hw_cm_per.h" // SYS-BIOS
#include "soc_AM335x.h" // SYS-BIOS

#define MMAP_OFFSET 0x44c00000
#define Clock_Div 0x2
#define RD_CYCLETIME 0xa*(Clock_Div+1)
#define WR_CYCLETIME 0x3*(Clock_Div+1)
//#define RD_ACCESSTIME 0x8*(Clock_Div+1)
#define RD_ACCESSTIME 0x8*(Clock_Div+1)

#define CSRD_OFFTIME 0xa*(Clock_Div+1)
#define CSWR_OFFTIME 0x3*(Clock_Div+1)

#define ADV_ONTIME 0x1*(Clock_Div+1)
#define ADVWR_OFFTIME 0x1*(Clock_Div+1)
#define ADVRD_OFFTIME 0x2*(Clock_Div+1)

#define OE_ONTIME 0x2*(Clock_Div+1)
#define OE_OFFTIME 0x9*(Clock_Div+1)


#define WE_ONTIME 0x1*(Clock_Div+1)
#define WE_OFFTIME 0x3*(Clock_Div+1)
// redefine HWREG macro to use MMAP result
#define HWREG(x) __mmapl[(x-MMAP_OFFSET)/4]
#define CM_DEVICE 0x44E00700

volatile ulong *__mmapl;

uint gpmc_init()
{
    ushort csNum = 1;
    uint temp = 0;


    //enable clock to GPMC module
    HWREG(SOC_PRCM_REGS + CM_PER_GPMC_CLKCTRL ) |=
                CM_PER_GPMC_CLKCTRL_MODULEMODE_ENABLE;
    //check to see if enabled
    while((HWREG(SOC_PRCM_REGS + CM_PER_GPMC_CLKCTRL) & CM_PER_GPMC_CLKCTRL_IDLEST) !=
                (CM_PER_GPMC_CLKCTRL_IDLEST_FUNC << CM_PER_GPMC_CLKCTRL_IDLEST_SHIFT));

    //reset the GPMC module
    HWREG(SOC_GPMC_0_REGS + GPMC_SYSCONFIG ) |= GPMC_SYSCONFIG_SOFTRESET;
    while((HWREG(SOC_GPMC_0_REGS + GPMC_SYSSTATUS) & GPMC_SYSSTATUS_RESETDONE) ==
                GPMC_SYSSTATUS_RESETDONE_RSTONGOING);

    //Configure to no idle
    temp = HWREG(SOC_GPMC_0_REGS + GPMC_SYSCONFIG);
    temp &= ~GPMC_SYSCONFIG_IDLEMODE;
    temp |= GPMC_SYSCONFIG_IDLEMODE_NOIDLE << GPMC_SYSCONFIG_IDLEMODE_SHIFT;
    HWREG(SOC_GPMC_0_REGS + GPMC_SYSCONFIG) = temp;

    HWREG(SOC_GPMC_0_REGS + GPMC_IRQENABLE) = 0x0;
    HWREG(SOC_GPMC_0_REGS + GPMC_TIMEOUT_CONTROL) = 0x0;

    //configure for NOR and granularity x2
    // CONFIG 1 .. 16 bits multiplexed
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG1(csNum)) = (0x0 |
        (GPMC_CONFIG1_0_DEVICESIZE_SIXTEENBITS <<
                GPMC_CONFIG1_0_DEVICESIZE_SHIFT ) |
        (GPMC_CONFIG1_0_ATTACHEDDEVICEPAGELENGTH_FOUR <<
                GPMC_CONFIG1_0_ATTACHEDDEVICEPAGELENGTH_SHIFT ) |
        (0x2 << 8 )|(0x28000000)|(Clock_Div));  //Address/Data Multiplex enable
    // config 2 .. chip select assert/deassert times
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG2(csNum)) = (0x0 |
        (0x00) |        // CS_ON_TIME  -- bigger than adv deassert..
        (CSRD_OFFTIME << GPMC_CONFIG2_0_CSRDOFFTIME_SHIFT) |    // CS_DEASSERT_RD
        (CSWR_OFFTIME << GPMC_CONFIG2_0_CSWROFFTIME_SHIFT));    //CS_DEASSERT_WR

    // config 3 .. latch enable assert and de-assert
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG3(csNum)) = (0x0 |
        (ADV_ONTIME << GPMC_CONFIG3_0_ADVONTIME_SHIFT) | //ADV_ASSERT
        (ADVRD_OFFTIME << GPMC_CONFIG3_0_ADVRDOFFTIME_SHIFT) | //ADV_DEASSERT_RD
        (ADVWR_OFFTIME << GPMC_CONFIG3_0_ADVWROFFTIME_SHIFT)); //ADV_DEASSERT_WR

    // config 4 .. output enable / read write enable assert and de-assert
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG4(csNum)) = (0x0 |
        (OE_ONTIME << GPMC_CONFIG4_0_OEONTIME_SHIFT) |  //OE_ASSERT
        (OE_OFFTIME << GPMC_CONFIG4_0_OEOFFTIME_SHIFT) |        //OE_DEASSERT
        (WE_ONTIME << GPMC_CONFIG4_0_WEONTIME_SHIFT)| //WE_ASSERT
        (WE_OFFTIME << GPMC_CONFIG4_0_WEOFFTIME_SHIFT)); //WE_DEASSERT
      (WE_OFFTIME << GPMC_CONFIG4_0_WEOFFTIME_SHIFT)); //WE_DEASSERT
    // Config 5 - read and write cycle time
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG5(csNum)) = (0x0 |
        (RD_CYCLETIME << GPMC_CONFIG5_0_RDCYCLETIME_SHIFT)|     //CFG_5_RD_CYCLE_TIM XXX
        (WR_CYCLETIME << GPMC_CONFIG5_0_WRCYCLETIME_SHIFT)|     //CFG_5_WR_CYCLE_TIM XXX
        //(OE_ONTIME  << GPMC_CONFIG5_0_RDACCESSTIME_SHIFT));  // CFG_5_RD_ACCESS_TIM XXX
        (RD_ACCESSTIME  << GPMC_CONFIG5_0_RDACCESSTIME_SHIFT));  // CFG_5_RD_ACCESS_TIM XXX

    // Config 6 .. bus turnaround delay, etc
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG6(csNum)) = (0x0 |
        (0 << //GPMC_CONFIG6_0_CYCLE2CYCLESAMECSEN_C2CDELAY
                GPMC_CONFIG6_0_CYCLE2CYCLESAMECSEN_SHIFT) |
        (0 << GPMC_CONFIG6_0_CYCLE2CYCLEDELAY_SHIFT) | //CYC2CYC_DELAY
        (OE_ONTIME << GPMC_CONFIG6_0_WRDATAONADMUXBUS_SHIFT)| //WR_DATA_ON_ADMUX XXX
        (0 << GPMC_CONFIG6_0_WRACCESSTIME_SHIFT));  //CFG_6_WR_ACCESS_TIM

    // config 7 .. base address of the chip select and address space. (16 MB is smallest)
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG7(csNum)) =
        ( 0x09 << GPMC_CONFIG7_0_BASEADDRESS_SHIFT) | //CFG_7_BASE_ADDR
        (0x1 << GPMC_CONFIG7_0_CSVALID_SHIFT) |
        (0x0f << GPMC_CONFIG7_0_MASKADDRESS_SHIFT);  //CFG_7_MASK

 printf("\n CONFIG1=0x%x", HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG1(csNum)));
 printf("\n CONFIG2=0x%x", HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG2(csNum)));
 printf("\n CONFIG3=0x%x", HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG3(csNum)));
 printf("\n CONFIG4=0x%x", HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG4(csNum)));
 printf("\n CONFIG50=0x%x", HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG5(csNum)));
 printf("\n CONFIG6=0x%x", HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG6(csNum)));
 printf("\n CONFIG7=0x%x", HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG7(csNum)));


    return 0;
}

ushort mymem[0x10000];

int main(int argc, char** argv)
{
    int i, k,temp;
    ushort testread_temp = 1;
    int j=0,addr=0x35a5;
          printf("\n testread_Temp Before: %x",testread_temp);

    int fd = open("/dev/mem", O_RDWR|O_SYNC); //O_SYNC makes the memory uncacheable
    __mmapl = (ulong*) mmap(NULL, 0x20000000, PROT_READ|PROT_WRITE, MAP_SHARED, fd, MMAP_OFFSET);

    gpmc_init();

   volatile ushort *extmem;

    extmem =(ushort *)mmap(NULL, 0x40000, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0x09000000);
    HWREG(CM_DEVICE) = 0x9b; //0xb1;// 0xA1; // Send L3 clock/5 = 40 Mhz to CLKOUT2

            printf("\n GPMC_SYSCONFIG=0x%x", HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG7(1)-0x58 ));
            printf("\n GPMC_STATUS=0x%x", HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG7(1)-0x54 ));

           i = 0x1a52;
          extmem[i] = 0x5a5a;
          extmem[i+1] = 0x5a5a;
          printf("\n testread_Temp After Write Before Read: %x",testread_temp);
           test_temp = extmem[0x1a52];
          temp=msync((void *)extmem,0x40000,MS_ASYNC);

          printf("\n sync result=%d testread_Temp: %x\n",temp,testread_temp);
    }
    return(0);
}

output:

 testread_Temp Before: 1
 CONFIG1=0x28001202
 CONFIG2=0x91e00
 CONFIG3=0x30603
 CONFIG4=0x9031b06
 CONFIG50=0x18091e
 CONFIG6=0x60000
 CONFIG7=0xf49
 GPMC_SYSCONFIG=0xa00
 GPMC_STATUS=0x1
 testread_Temp After Write Before Read: 1
 sync result=0 testread_Temp: 0