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sun50iw1p1-clk.dtsi

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  1. /{
  2. clocks {
  3. compatible = "allwinner,sunxi-clk-init";
  4. device_type = "clocks";
  5. #address-cells = <2>;
  6. #size-cells = <2>;
  7. ranges;
  8. reg = <0x0 0x01c20000 0x0 0x0320> , /*cpux space*/
  9. <0x0 0x01f01400 0x0 0x00B0> , /*cpus space*/
  10. <0x0 0x01f00060 0x0 0x4>;
  11. /* register fixed rate clock*/
  12. clk_losc: losc {
  13. #clock-cells = <0>;
  14. compatible = "allwinner,fixed-clock";
  15. clock-frequency = <32768>;
  16. clock-output-names = "losc";
  17. };
  18.  
  19. clk_iosc: iosc {
  20. #clock-cells = <0>;
  21. compatible = "allwinner,fixed-clock";
  22. clock-frequency = <16000000>;
  23. clock-output-names = "iosc";
  24. };
  25.  
  26. clk_hosc: hosc {
  27. #clock-cells = <0>;
  28. compatible = "allwinner,fixed-clock";
  29. clock-frequency = <24000000>;
  30. clock-output-names = "hosc";
  31. };
  32. /* register allwinner,sunxi-pll-clock */
  33. clk_pll_cpu: pll_cpu {
  34. #clock-cells = <0>;
  35. compatible = "allwinner,sunxi-pll-clock";
  36. lock-mode = "new";
  37. clock-output-names = "pll_cpu";
  38. };
  39. clk_pll_audio: pll_audio {
  40. #clock-cells = <0>;
  41. compatible = "allwinner,sunxi-pll-clock";
  42. lock-mode = "new";
  43. clock-output-names = "pll_audio";
  44. };
  45. clk_pll_video0: pll_video0 {
  46. #clock-cells = <0>;
  47. compatible = "allwinner,sunxi-pll-clock";
  48. lock-mode = "new";
  49. assigned-clock-rates = <297000000>;
  50. clock-output-names = "pll_video0";
  51. };
  52. clk_pll_ve: pll_ve {
  53. #clock-cells = <0>;
  54. compatible = "allwinner,sunxi-pll-clock";
  55. lock-mode = "new";
  56. clock-output-names = "pll_ve";
  57. };
  58. clk_pll_ddr0: pll_ddr0 {
  59. #clock-cells = <0>;
  60. compatible = "allwinner,sunxi-pll-clock";
  61. lock-mode = "new";
  62. clock-output-names = "pll_ddr0";
  63. };
  64. clk_pll_periph0: pll_periph0 {
  65. #clock-cells = <0>;
  66. compatible = "allwinner,sunxi-pll-clock";
  67. lock-mode = "new";
  68. clock-output-names = "pll_periph0";
  69. };
  70. clk_pll_periph1: pll_periph1 {
  71. #clock-cells = <0>;
  72. compatible = "allwinner,sunxi-pll-clock";
  73. lock-mode = "new";
  74. clock-output-names = "pll_periph1";
  75. };
  76. clk_pll_video1: pll_video1 {
  77. #clock-cells = <0>;
  78. compatible = "allwinner,sunxi-pll-clock";
  79. lock-mode = "new";
  80. assigned-clock-rates = <297000000>;
  81. clock-output-names = "pll_video1";
  82. };
  83. clk_pll_gpu: pll_gpu {
  84. #clock-cells = <0>;
  85. compatible = "allwinner,sunxi-pll-clock";
  86. lock-mode = "new";
  87. clock-output-names = "pll_gpu";
  88. };
  89. clk_pll_mipi: pll_mipi {
  90. #clock-cells = <0>;
  91. compatible = "allwinner,sunxi-pll-clock";
  92. lock-mode = "new";
  93. clock-output-names = "pll_mipi";
  94. };
  95. clk_pll_hsic: pll_hsic {
  96. #clock-cells = <0>;
  97. compatible = "allwinner,sunxi-pll-clock";
  98. lock-mode = "new";
  99. clock-output-names = "pll_hsic";
  100. };
  101. clk_pll_de: pll_de {
  102. #clock-cells = <0>;
  103. compatible = "allwinner,sunxi-pll-clock";
  104. lock-mode = "new";
  105. assigned-clock-rates = <297000000>;
  106. clock-output-names = "pll_de";
  107. };
  108. clk_pll_ddr1: pll_ddr1 {
  109. #clock-cells = <0>;
  110. compatible = "allwinner,sunxi-pll-clock";
  111. lock-mode = "new";
  112. clock-output-names = "pll_ddr1";
  113. };
  114. /* register fixed factor clock*/
  115. clk_pll_audiox8: pll_audiox8 {
  116. #clock-cells = <0>;
  117. compatible = "allwinner,fixed-factor-clock";
  118. clocks = <&clk_pll_audio>;
  119. clock-mult = <8>;
  120. clock-div = <1>;
  121. clock-output-names = "pll_audiox8";
  122. };
  123. clk_pll_audiox4: pll_audiox4 {
  124. #clock-cells = <0>;
  125. compatible = "allwinner,fixed-factor-clock";
  126. clocks = <&clk_pll_audio>;
  127. clock-mult = <8>;
  128. clock-div = <2>;
  129. clock-output-names = "pll_audiox4";
  130. };
  131. clk_pll_audiox2: pll_audiox2 {
  132. #clock-cells = <0>;
  133. compatible = "allwinner,fixed-factor-clock";
  134. clocks = <&clk_pll_audio>;
  135. clock-mult = <8>;
  136. clock-div = <4>;
  137. clock-output-names = "pll_audiox2";
  138. };
  139. clk_pll_video0x2: pll_video0x2 {
  140. #clock-cells = <0>;
  141. compatible = "allwinner,fixed-factor-clock";
  142. clocks = <&clk_pll_video0>;
  143. clock-mult = <2>;
  144. clock-div = <1>;
  145. clock-output-names = "pll_video0x2";
  146. };
  147. clk_pll_periph0x2: pll_periph0x2 {
  148. #clock-cells = <0>;
  149. compatible = "allwinner,fixed-factor-clock";
  150. clocks = <&clk_pll_periph0>;
  151. clock-mult = <2>;
  152. clock-div = <1>;
  153. clock-output-names = "pll_periph0x2";
  154. };
  155. clk_pll_periph1x2: pll_periph1x2 {
  156. #clock-cells = <0>;
  157. compatible = "allwinner,fixed-factor-clock";
  158. clocks = <&clk_pll_periph1>;
  159. clock-mult = <2>;
  160. clock-div = <1>;
  161. clock-output-names = "pll_periph1x2";
  162. };
  163. clk_pll_periph0d2: pll_periph0d2 {
  164. #clock-cells = <0>;
  165. compatible = "allwinner,fixed-factor-clock";
  166. clocks = <&clk_pll_periph0>;
  167. clock-mult = <1>;
  168. clock-div = <2>;
  169. clock-output-names = "pll_periph0d2";
  170. };
  171. clk_hoscd2: hoscd2 {
  172. #clock-cells = <0>;
  173. compatible = "allwinner,fixed-factor-clock";
  174. clocks = <&clk_hosc>;
  175. clock-mult = <1>;
  176. clock-div = <2>;
  177. clock-output-names = "hoscd2";
  178. };
  179. /* register allwinner,sunxi-periph-clock */
  180. clk_cpu: cpu {
  181. #clock-cells = <0>;
  182. compatible = "allwinner,sunxi-periph-clock";
  183. clock-output-names = "cpu";
  184. };
  185. clk_cpuapb: cpuapb {
  186. #clock-cells = <0>;
  187. compatible = "allwinner,sunxi-periph-clock";
  188. clock-output-names = "cpuapb";
  189. };
  190. clk_axi: axi {
  191. #clock-cells = <0>;
  192. compatible = "allwinner,sunxi-periph-clock";
  193. clock-output-names = "axi";
  194. };
  195. clk_pll_periphahb0: pll_periphahb0 {
  196. #clock-cells = <0>;
  197. compatible = "allwinner,sunxi-periph-clock";
  198. clock-output-names = "pll_periphahb0";
  199. };
  200. clk_ahb1: ahb1 {
  201. #clock-cells = <0>;
  202. compatible = "allwinner,sunxi-periph-clock";
  203. clock-output-names = "ahb1";
  204. };
  205. clk_apb1: apb1 {
  206. #clock-cells = <0>;
  207. compatible = "allwinner,sunxi-periph-clock";
  208. clock-output-names = "apb1";
  209. };
  210. clk_apb2: apb2 {
  211. #clock-cells = <0>;
  212. compatible = "allwinner,sunxi-periph-clock";
  213. clock-output-names = "apb2";
  214. };
  215. clk_ahb2: ahb2 {
  216. #clock-cells = <0>;
  217. compatible = "allwinner,sunxi-periph-clock";
  218. clock-output-names = "ahb2";
  219. };
  220. clk_ths: ths {
  221. #clock-cells = <0>;
  222. compatible = "allwinner,sunxi-periph-clock";
  223. clock-output-names = "ths";
  224. };
  225. clk_nand: nand {
  226. #clock-cells = <0>;
  227. compatible = "allwinner,sunxi-periph-clock";
  228. clock-output-names = "nand";
  229. };
  230. clk_sdmmc0_mod: sdmmc0_mod {
  231. #clock-cells = <0>;
  232. compatible = "allwinner,sunxi-periph-clock";
  233. clock-output-names = "sdmmc0_mod";
  234. };
  235. clk_sdmmc0_bus: sdmmc0_bus {
  236. #clock-cells = <0>;
  237. compatible = "allwinner,sunxi-periph-clock";
  238. clock-output-names = "sdmmc0_bus";
  239. };
  240. clk_sdmmc0_rst: sdmmc0_rst {
  241. #clock-cells = <0>;
  242. compatible = "allwinner,sunxi-periph-clock";
  243. clock-output-names = "sdmmc0_rst";
  244. };
  245.  
  246. clk_sdmmc1_mod: sdmmc1_mod {
  247. #clock-cells = <0>;
  248. compatible = "allwinner,sunxi-periph-clock";
  249. clock-output-names = "sdmmc1_mod";
  250. };
  251. clk_sdmmc1_bus: sdmmc1_bus {
  252. #clock-cells = <0>;
  253. compatible = "allwinner,sunxi-periph-clock";
  254. clock-output-names = "sdmmc1_bus";
  255. };
  256. clk_sdmmc1_rst: sdmmc1_rst {
  257. #clock-cells = <0>;
  258. compatible = "allwinner,sunxi-periph-clock";
  259. clock-output-names = "sdmmc1_rst";
  260. };
  261. clk_sdmmc2_mod: sdmmc2_mod {
  262. #clock-cells = <0>;
  263. compatible = "allwinner,sunxi-periph-clock";
  264. clock-output-names = "sdmmc2_mod";
  265. };
  266. clk_sdmmc2_bus: sdmmc2_bus {
  267. #clock-cells = <0>;
  268. compatible = "allwinner,sunxi-periph-clock";
  269. clock-output-names = "sdmmc2_bus";
  270. };
  271. clk_sdmmc2_rst: sdmmc2_rst {
  272. #clock-cells = <0>;
  273. compatible = "allwinner,sunxi-periph-clock";
  274. clock-output-names = "sdmmc2_rst";
  275. };
  276. clk_ts: ts {
  277. #clock-cells = <0>;
  278. compatible = "allwinner,sunxi-periph-clock";
  279. clock-output-names = "ts";
  280. };
  281. clk_ce: ce {
  282. #clock-cells = <0>;
  283. compatible = "allwinner,sunxi-periph-clock";
  284. clock-output-names = "ce";
  285. };
  286. clk_spi0: spi0 {
  287. #clock-cells = <0>;
  288. compatible = "allwinner,sunxi-periph-clock";
  289. clock-output-names = "spi0";
  290. };
  291. clk_spi1: spi1 {
  292. #clock-cells = <0>;
  293. compatible = "allwinner,sunxi-periph-clock";
  294. clock-output-names = "spi1";
  295. };
  296. clk_i2s0: i2s0 {
  297. #clock-cells = <0>;
  298. compatible = "allwinner,sunxi-periph-clock";
  299. clock-output-names = "i2s0";
  300. };
  301. clk_i2s1: i2s1 {
  302. #clock-cells = <0>;
  303. compatible = "allwinner,sunxi-periph-clock";
  304. clock-output-names = "i2s1";
  305. };
  306. clk_i2s2: i2s2 {
  307. #clock-cells = <0>;
  308. compatible = "allwinner,sunxi-periph-clock";
  309. clock-output-names = "i2s2";
  310. };
  311. clk_spdif: spdif {
  312. #clock-cells = <0>;
  313. compatible = "allwinner,sunxi-periph-clock";
  314. clock-output-names = "spdif";
  315. };
  316. clk_usbphy0: usbphy0 {
  317. #clock-cells = <0>;
  318. compatible = "allwinner,sunxi-periph-clock";
  319. clock-output-names = "usbphy0";
  320. };
  321. clk_usbphy1: usbphy1 {
  322. #clock-cells = <0>;
  323. compatible = "allwinner,sunxi-periph-clock";
  324. clock-output-names = "usbphy1";
  325. };
  326. clk_usbhsic: usbhsic {
  327. #clock-cells = <0>;
  328. compatible = "allwinner,sunxi-periph-clock";
  329. clock-output-names = "usbhsic";
  330. };
  331. clk_usbhsic12m: usbhsic12m {
  332. #clock-cells = <0>;
  333. compatible = "allwinner,sunxi-periph-clock";
  334. clock-output-names = "usbhsic12m";
  335. };
  336. clk_usbohci1: usbohci1 {
  337. #clock-cells = <0>;
  338. compatible = "allwinner,sunxi-periph-clock";
  339. clock-output-names = "usbohci1";
  340. };
  341. clk_usbohci0: usbohci0 {
  342. #clock-cells = <0>;
  343. compatible = "allwinner,sunxi-periph-clock";
  344. clock-output-names = "usbohci0";
  345. };
  346. clk_de: de {
  347. #clock-cells = <0>;
  348. compatible = "allwinner,sunxi-periph-clock";
  349. assigned-clock-parents = <&clk_pll_de>;
  350. assigned-clock-rates = <297000000>;
  351. clock-output-names = "de";
  352. };
  353. clk_tcon0: tcon0 {
  354. #clock-cells = <0>;
  355. compatible = "allwinner,sunxi-periph-clock";
  356. assigned-clock-parents = <&clk_pll_mipi>;
  357. clock-output-names = "tcon0";
  358. };
  359. clk_tcon1: tcon1 {
  360. #clock-cells = <0>;
  361. compatible = "allwinner,sunxi-periph-clock";
  362. assigned-clock-parents = <&clk_pll_video0>;
  363. clock-output-names = "tcon1";
  364. };
  365. clk_deinterlace: deinterlace {
  366. #clock-cells = <0>;
  367. compatible = "allwinner,sunxi-periph-clock";
  368. clock-output-names = "deinterlace";
  369. };
  370. clk_csi_s: csi_s {
  371. #clock-cells = <0>;
  372. compatible = "allwinner,sunxi-periph-clock";
  373. clock-output-names = "csi_s";
  374. };
  375. clk_csi_m: csi_m {
  376. #clock-cells = <0>;
  377. compatible = "allwinner,sunxi-periph-clock";
  378. clock-output-names = "csi_m";
  379. };
  380. clk_csi_misc: csi_misc {
  381. #clock-cells = <0>;
  382. compatible = "allwinner,sunxi-periph-clock";
  383. clock-output-names = "csi_misc";
  384. };
  385. clk_ve: ve {
  386. #clock-cells = <0>;
  387. compatible = "allwinner,sunxi-periph-clock";
  388. clock-output-names = "ve";
  389. };
  390. clk_adda: adda {
  391. #clock-cells = <0>;
  392. compatible = "allwinner,sunxi-periph-clock";
  393. clock-output-names = "adda";
  394. };
  395. clk_addax4: addax4 {
  396. #clock-cells = <0>;
  397. compatible = "allwinner,sunxi-periph-clock";
  398. clock-output-names = "addax4";
  399. };
  400. clk_avs: avs {
  401. #clock-cells = <0>;
  402. compatible = "allwinner,sunxi-periph-clock";
  403. clock-output-names = "avs";
  404. };
  405. clk_hdmi: hdmi {
  406. #clock-cells = <0>;
  407. compatible = "allwinner,sunxi-periph-clock";
  408. assigned-clock-parents = <&clk_pll_video0>;
  409. clock-output-names = "hdmi";
  410. };
  411. clk_hdmi_slow: hdmi_slow {
  412. #clock-cells = <0>;
  413. compatible = "allwinner,sunxi-periph-clock";
  414. clock-output-names = "hdmi_slow";
  415. };
  416. clk_mbus: mbus {
  417. #clock-cells = <0>;
  418. compatible = "allwinner,sunxi-periph-clock";
  419. clock-output-names = "mbus";
  420. };
  421. clk_mipidsi: mipidsi {
  422. #clock-cells = <0>;
  423. compatible = "allwinner,sunxi-periph-clock";
  424. clock-output-names = "mipidsi";
  425. };
  426. clk_gpu: gpu {
  427. #clock-cells = <0>;
  428. compatible = "allwinner,sunxi-periph-clock";
  429. clock-output-names = "gpu";
  430. };
  431. clk_usbohci_16: usbehci_16 {
  432. #clock-cells = <0>;
  433. compatible = "allwinner,sunxi-periph-clock";
  434. clock-output-names = "usbohci_16";
  435. };
  436. clk_usbehci1: usbehci1 {
  437. #clock-cells = <0>;
  438. compatible = "allwinner,sunxi-periph-clock";
  439. clock-output-names = "usbehci1";
  440. };
  441. clk_usbehci0: usbehci0 {
  442. #clock-cells = <0>;
  443. compatible = "allwinner,sunxi-periph-clock";
  444. clock-output-names = "usbehci0";
  445. };
  446. clk_usbotg: usbotg {
  447. #clock-cells = <0>;
  448. compatible = "allwinner,sunxi-periph-clock";
  449. clock-output-names = "usbotg";
  450. };
  451. clk_gmac: gmac {
  452. #clock-cells = <0>;
  453. compatible = "allwinner,sunxi-periph-clock";
  454. clock-output-names = "gmac";
  455. };
  456. clk_sdram: sdram {
  457. #clock-cells = <0>;
  458. compatible = "allwinner,sunxi-periph-clock";
  459. clock-output-names = "sdram";
  460. };
  461. clk_dma: dma {
  462. #clock-cells = <0>;
  463. compatible = "allwinner,sunxi-periph-clock";
  464. clock-output-names = "dma";
  465. };
  466. clk_hwspinlock_rst: hwspinlock_rst {
  467. #clock-cells = <0>;
  468. compatible = "allwinner,sunxi-periph-clock";
  469. clock-output-names = "hwspinlock_rst";
  470. };
  471. clk_hwspinlock_bus: hwspinlock_bus {
  472. #clock-cells = <0>;
  473. compatible = "allwinner,sunxi-periph-clock";
  474. clock-output-names = "hwspinlock_bus";
  475. };
  476. clk_msgbox: msgbox {
  477. #clock-cells = <0>;
  478. compatible = "allwinner,sunxi-periph-clock";
  479. clock-output-names = "msgbox";
  480. };
  481. clk_lvds: lvds {
  482. #clock-cells = <0>;
  483. compatible = "allwinner,sunxi-periph-clock";
  484. clock-output-names = "lvds";
  485. };
  486. clk_uart0: uart0 {
  487. #clock-cells = <0>;
  488. compatible = "allwinner,sunxi-periph-clock";
  489. clock-output-names = "uart0";
  490. };
  491. clk_uart1: uart1 {
  492. #clock-cells = <0>;
  493. compatible = "allwinner,sunxi-periph-clock";
  494. clock-output-names = "uart1";
  495. };
  496. clk_uart2: uart2 {
  497. #clock-cells = <0>;
  498. compatible = "allwinner,sunxi-periph-clock";
  499. clock-output-names = "uart2";
  500. };
  501. clk_uart3: uart3 {
  502. #clock-cells = <0>;
  503. compatible = "allwinner,sunxi-periph-clock";
  504. clock-output-names = "uart3";
  505. };
  506. clk_uart4: uart4 {
  507. #clock-cells = <0>;
  508. compatible = "allwinner,sunxi-periph-clock";
  509. clock-output-names = "uart4";
  510. };
  511. clk_scr: scr {
  512. #clock-cells = <0>;
  513. compatible = "allwinner,sunxi-periph-clock";
  514. clock-output-names = "scr";
  515. };
  516. clk_twi0: twi0 {
  517. #clock-cells = <0>;
  518. compatible = "allwinner,sunxi-periph-clock";
  519. clock-output-names = "twi0";
  520. };
  521. clk_twi1: twi1 {
  522. #clock-cells = <0>;
  523. compatible = "allwinner,sunxi-periph-clock";
  524. clock-output-names = "twi1";
  525. };
  526. clk_twi2: twi2 {
  527. #clock-cells = <0>;
  528. compatible = "allwinner,sunxi-periph-clock";
  529. clock-output-names = "twi2";
  530. };
  531. clk_twi3: twi3 {
  532. #clock-cells = <0>;
  533. compatible = "allwinner,sunxi-periph-clock";
  534. clock-output-names = "twi3";
  535. };
  536. clk_pio: pio {
  537. #clock-cells = <0>;
  538. compatible = "allwinner,sunxi-periph-clock";
  539. clock-output-names = "pio";
  540. };
  541. /*cpus space clocks from PRCM-SPEC*/
  542. clk_cpurcir: cpurcir {
  543. #clock-cells = <0>;
  544. compatible = "allwinner,sunxi-periph-cpus-clock";
  545. clock-output-names = "cpurcir";
  546. };
  547. clk_cpurpio: cpurpio {
  548. #clock-cells = <0>;
  549. compatible = "allwinner,sunxi-periph-cpus-clock";
  550. clock-output-names = "cpurpio";
  551. };
  552. /* "cpurpll_peri0 cpurcpus cpurahbs cpurapbs" are read only , just to keep a clock tree */
  553. clk_cpurpll_peri0: cpurpll_peri0 {
  554. #clock-cells = <0>;
  555. compatible = "allwinner,sunxi-periph-cpus-clock";
  556. clock-output-names = "cpurpll_peri0";
  557. };
  558. clk_cpurcpus: cpurcpus {
  559. #clock-cells = <0>;
  560. compatible = "allwinner,sunxi-periph-cpus-clock";
  561. clock-output-names = "cpurcpus";
  562. };
  563. clk_cpurahbs: cpurahbs {
  564. #clock-cells = <0>;
  565. compatible = "allwinner,sunxi-periph-cpus-clock";
  566. clock-output-names = "cpurahbs";
  567. };
  568. clk_cpurapbs: cpurapbs {
  569. #clock-cells = <0>;
  570. compatible = "allwinner,sunxi-periph-cpus-clock";
  571. clock-output-names = "cpurapbs";
  572. };
  573. clk_losc_out: losc_out {
  574. #clock-cells = <0>;
  575. compatible = "allwinner,sunxi-periph-cpus-clock";
  576. clock-output-names = "losc_out";
  577. };
  578. };/*clocks end*/
  579. };
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