instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
  match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
  predicate(UseBMI1Instructions);
  effect(KILL cr);

  ins_cost(125);
  format %{ "andnl  $dst, $src1, $src2" %}

  ins_encode %{
    __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
  %}
  ins_pipe(ialu_reg_mem);
%}