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May 6th, 2016
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VHDL 0.76 KB | None | 0 0
  1. library ieee;
  2.     use ieee.std_logic_1164.ALL;
  3.     use ieee.numeric_std.ALL;
  4.    
  5.        
  6. -- Jednostka licznika od 0 do target   
  7. entity PositiveCounter is
  8.     generic (
  9.         target: positive := 1000000
  10.     );
  11.    
  12.     port (
  13.         clk_in: IN STD_LOGIC;
  14.         enabled: IN STD_LOGIC;
  15.         Q: OUT STD_LOGIC;
  16.         reset: IN STD_LOGIC
  17.     );
  18. end entity;
  19.  
  20. -- Implementacja licznika
  21. architecture PositiveCounterImpl of PositiveCounter is
  22. begin
  23.     process (clk_in)
  24.         variable clkCounter : integer range 0 to target;
  25.     begin
  26.         if (rising_edge(clk_in)) then
  27.             if (reset = '1') then
  28.                 clkCounter := 0;
  29.             elsif (enabled = '1' and clkCounter < target) then
  30.                 clkCounter := clkCounter + 1;
  31.             end if;
  32.            
  33.            
  34.             Q <= '1' when (clkCounter = target) else '0';
  35.         end if;
  36.     end process;
  37. end architecture;
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