architecture behavior of FlipFlop is
signal tmp : std_logic;

begin
	tmp <= '0';
	process (CLK)
	begin
		Q <= tmp;
		tmp <= D;
	end process;
end architecture;

architecture behavior of PipedMul is

component FlipFlip is
     port (
	 	D : in std_logic;
	 	ClK : in std_logic;
	 	Q : out std_logic
	   );
end component;

begin


end architecture;