libray IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;


entity trigger is
	port(data: in std_logic,
		reset: in std_logic,
		klok: in std_logic,
		partroon: in std_logic_vector(7 downto 0)
		actie: out std_logic
	);
end trigger;

architecture tr of trigger is
begin
	process(klok)
	variable sign_val: std_logic := 0;
	variable teller: integer'range(8)
	begin
		if sign_val = data then
			teller = teller + 1;
			if teller > 7 then
				actie <= 1;
			end if;
		else
			sign_val := data;
			teller := 0;
		end if;
		if reset = 1 then
			actie <= 0;
		end if;
	end process;
end tr;