compas3

#include <stm32f10x.h>
#include "DWLOS_config.h"
#include "DWLOS.h"

#define  __INITh
#include "Init.h"
#include "i2c_interrupt.h"
#include "z_S65.h"


void initAll ()
 {
  SystemInit ();

//  RCC_Configuration
  RCC -> APB2ENR |= RCC_APB2ENR_IOPAEN |
                    RCC_APB2ENR_IOPBEN |
                    RCC_APB2ENR_AFIOEN |
                    RCC_APB2ENR_SPI1EN;


//  GPIO_Configuration
  // TIM2 CH2 = PA1
  GPIOA -> CRL |= GPIO_CRL_CNF1_1;
  GPIOA -> CRL &= ~GPIO_CRL_CNF1_0; // 0
  GPIOA -> CRL |= GPIO_CRL_MODE1_1 | GPIO_CRL_MODE1_0;

  // (RS) = PA2
  GPIOA -> CRL &= ~GPIO_CRL_CNF2_1;
  GPIOA -> CRL &= ~GPIO_CRL_CNF2_0;
  GPIOA -> CRL |= GPIO_CRL_MODE2_1 | GPIO_CRL_MODE2_0;

  // (RESET) = PA3
  GPIOA -> CRL &= ~GPIO_CRL_CNF3_1;
  GPIOA -> CRL &= ~GPIO_CRL_CNF3_0;
  GPIOA -> CRL |= GPIO_CRL_MODE3_1 | GPIO_CRL_MODE3_0;
  GPIOA -> BSRR |= GPIO_BSRR_BS3;

  // SPI1.NSS (CS) = PA4
  GPIOA -> CRL &= ~GPIO_CRL_CNF4_1; //1
  GPIOA -> CRL &= ~GPIO_CRL_CNF4_0;
  GPIOA -> CRL |= GPIO_CRL_MODE4_1 | GPIO_CRL_MODE4_0;
  GPIOA -> BSRR |= GPIO_BSRR_BS4;

  // SPI1.CLK (CLK) = PA5
  GPIOA -> CRL |= GPIO_CRL_CNF5_1;
  GPIOA -> CRL &= ~GPIO_CRL_CNF5_0;
  GPIOA -> CRL |= GPIO_CRL_MODE5_1 | GPIO_CRL_MODE5_0;

  // SPI1.MOSI (DAT) = PA7
  GPIOA -> CRL |= GPIO_CRL_CNF7_1;
  GPIOA -> CRL &= ~GPIO_CRL_CNF7_0;
  GPIOA -> CRL |= GPIO_CRL_MODE7_1 | GPIO_CRL_MODE7_0;

  // SPI1.MISO = PA6
  GPIOA -> CRL |= GPIO_CRL_CNF6_1;
  GPIOA -> CRL &= ~GPIO_CRL_CNF6_0;
  GPIOA -> CRL |= GPIO_CRL_MODE6_1 | GPIO_CRL_MODE6_0;

// PB0 -- Button 1
  GPIOB -> CRL &= ~GPIO_CRL_CNF0_1;
  GPIOB -> CRL |= GPIO_CRL_CNF0_0;
  GPIOB -> CRL &= ~(GPIO_CRL_MODE0_1 | GPIO_CRL_MODE0_0);
  GPIOB -> BSRR |= GPIO_BSRR_BR0;

  // PB1 -- Button 2
  GPIOB -> CRL &= ~GPIO_CRL_CNF1_1;
  GPIOB -> CRL |= GPIO_CRL_CNF1_0;
  GPIOB -> CRL &= ~(GPIO_CRL_MODE1_1 | GPIO_CRL_MODE1_0);
  GPIOB -> BSRR |= GPIO_BSRR_BR1;

  // PB10 -- Button 3
  GPIOB -> CRH &= ~GPIO_CRH_CNF10_1;
  GPIOB -> CRH |= GPIO_CRH_CNF10_0;
  GPIOB -> CRH &= ~(GPIO_CRH_MODE10_1 | GPIO_CRH_MODE10_0);
  GPIOB -> BSRR |= GPIO_BSRR_BR10;// */


  // Disable JTAG and SWD pins
  AFIO -> MAPR |= AFIO_MAPR_SWJ_CFG_DISABLE;





// upTime Timer
  RCC -> APB1ENR |= RCC_APB1ENR_TIM2EN;

  TIM2 -> CR1 &= ~(TIM_CR1_CKD_1 | TIM_CR1_CKD_0);  // Clock division
  TIM2 -> CR1 &= ~(TIM_CR1_CMS_1 | TIM_CR1_CMS_0);  // Center-aligned mode
  TIM2 -> CR1 &= ~(TIM_CR1_DIR);            // Direction - UP
  TIM2 -> CR1 |= TIM_CR1_ARPE;              // Autoreload
  TIM2 -> ARR = 10000;                  // Max value
  TIM2 -> PSC = 36000;                  // Prescalar
  TIM2 -> EGR = TIM_EGR_TG | TIM_EGR_UG;        // Load ARR to snacke registers

  /*/ OC1
  TIM2 -> CCMR1 &= ~(TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2);
  TIM2 -> CCMR1 |= TIM_CCMR1_OC1M_0;
  TIM2 -> CCER |= TIM_CCER_CC1E;
  TIM2 -> CCR1 = 500;// */

  TIM2 -> DIER |= TIM_DIER_UIE;     // TIM IT enable
  TIM2 -> CR1 |= TIM_CR1_CEN;       // TIM2 enable counter

  NVIC_SetPriority (TIM2_IRQn, 0);
  NVIC_EnableIRQ (TIM2_IRQn);






//  NVIC_Configuration
  NVIC_SetPriority (DMA1_Channel3_IRQn, 7); // SPI1 TX
  NVIC_EnableIRQ (DMA1_Channel3_IRQn);


  I2C1_init (I2C_REMAP);
//  I2C2_init ();





// DMA1 Channel3 -- SPI
  SPI_Tx_DMA -> CCR &= ~DMA_CCR3_MEM2MEM;
  SPI_Tx_DMA -> CCR |= DMA_CCR3_PL_1 | DMA_CCR3_PL_0;
  SPI_Tx_DMA -> CCR &= ~DMA_CCR3_MSIZE_1;
  SPI_Tx_DMA -> CCR |= DMA_CCR3_MSIZE_0;
  SPI_Tx_DMA -> CCR &= ~DMA_CCR3_PSIZE_1;
  SPI_Tx_DMA -> CCR |= DMA_CCR3_PSIZE_0;
  SPI_Tx_DMA -> CCR |= DMA_CCR3_MINC;
  SPI_Tx_DMA -> CCR &= ~DMA_CCR3_PINC;
  SPI_Tx_DMA -> CCR &= ~DMA_CCR3_CIRC;
  SPI_Tx_DMA -> CCR |= DMA_CCR3_DIR;
  SPI_Tx_DMA -> CPAR = (uint32_t) (SPI1_BASE + 0x0C);
//  SPI_Tx_DMA -> CCR |= DMA_CCR3_TCIE;


// SPI Configuration
//  SPI1 -> CR1 |= SPI_CR1_BIDIMODE;
//  SPI1 -> CR1 |= SPI_CR1_BIDIOE;
  SPI1 -> CR1 &= ~SPI_CR1_CRCEN;
  SPI1 -> CR1 |= SPI_CR1_DFF;
//    SPI1 -> CR1 |= SPI_CR1_BR_2;
    SPI1 -> CR1 |= SPI_CR1_BR_1;
//    SPI1 -> CR1 |= SPI_CR1_BR_0;
  SPI1 -> CR1 |= SPI_CR1_SSM;
  SPI1 -> CR1 |= SPI_CR1_SSI;
  SPI1 -> CR1 |= SPI_CR1_MSTR;
  SPI1 -> CR1 &= ~SPI_CR1_CPOL;
  SPI1 -> CR1 &= ~SPI_CR1_CPHA;
//  SPI1 -> CR2 |= SPI_CR2_SSOE;
//  SPI1 -> CR2 |= SPI_CR2_TXDMAEN;
  SPI1 -> CR1 |= SPI_CR1_SPE;

 }