module licznik(CLK, CLR, OUT, CE);
input CLK, CLR, CE;
output [3:0]OUT;

reg [3:0]OUT;

always @(posedge CLK or negedge CLR)
begin

if(!CLR)
OUT <= 4'b0000;
else
    if(CE)
        OUT<=OUT+1;
end

endmodule

////////////////////////////////////////////////////////////////////////////////
module preskaler(CLK,CLR,CE,Q,CEO);
input CLK, CLR, CE;
output reg [27:0] Q;
output CEO;

always @(posedge CLK or negedge CLR)
begin
if(!CLR)
Q <= 28'd0;
else
if(CE)
if(Q != 28'd99999999)
Q <= Q + 1;
else
Q <= 28'd0;
end

assign CEO = CE & (Q == 28'd99999999);

endmodule
///////////////////////////////////////////////////////////////////////////////
module polaczenie(CLK, CLR, CE, Q, CEO, OUT);

input CLK, CLR, CE;
output [27:0]Q;
output [3:0]OUT;
output CEO;

//module preskaler(CLK,CLR,CE,Q,CEO);
preskaler dzielnik(CLK, CLR, 1'b1, Q, CEO);

//module licznik(CLK, CLR, OUT, CE);
licznik licz(CLK, CLR, OUT, CEO);

endmodule