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-- Company:
-- Engineer:
--
-- Create Date:    22:19:55 02/26/2016
-- Design Name:
-- Module Name:    UpDownCounter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity UpDownCounter is
    Generic(   N : integer := 4;        -- Use of generics to make port declarations more flexible.
                M : integer := 10);     -- M is not used in this project, but will be used in further examples.
    Port ( CLK, CLR, DIRECTION, ENABLE : in  STD_LOGIC;
                LED : out  STD_LOGIC_VECTOR(N-1 downto 0));
end UpDownCounter;

architecture Behavioral of UpDownCounter is
--  signal count: std_logic_vector(N-1 downto 0);   -- NOTE: if you uncomment this line, you should comment line 45, and
                                                            -- uncomment line 70 and comment line 71. In this case,
                                                            --  you don't need the package "IEEE.NUMERIC_STD.ALL" declared on line 23.
    signal count: unsigned(N-1 downto 0) := (others => '0');                    -- Initialization is very important!
    signal prescaler : std_logic_vector(26 downto 0) := (others => '0');    -- The prescaler is used to implement a clock divider.
begin
    countProc: process (CLK, CLR)
    begin
        if CLR ='1' then
            count <= (others => '0');
        else
--          if (CLK'event and CLK = '1') then -- Tracks the transition from low to high in the clock signal. Similar to
--          if rising_edge(CLK) then
--          if (CLK'event and CLK = '0') then -- Tracks the transition from high to low in the clock signal. Similar to
            if falling_edge(CLK) then
--              if prescaler = "101111101011110000100000000" then   -- checking if the prescaler has reached 100 000 000, 100Mhz.
                if prescaler = x"5F5E100" then  -- The same using Hexadecimal notation.
--              if prescaler = "000101000000000000000000000" then   -- checking if the prescaler has reached 50 000 000, 50Mhz.
                    prescaler <= (others => '0');                       -- If so, then we set it to zero, and
                    if ENABLE = '0' and DIRECTION = '0' then        --  if ENABLE and DIRECTION are both '0',
                        count <= count + 1;                             -- we increment the couter, else
                    elsif ENABLE = '0' and DIRECTION = '1' then     -- if ENABLE is '0' and DIRECTION '1',
                        count <= count - 1;                                 -- we decrement the counter.
                    end if;
                else
                    prescaler <= prescaler + 1;     -- Increment the prescaler case it is less then 100 000 000.
                end if;
            end if;
        end if;
    end process;
--  LED <= count;   -- Typecasting is not necessary if count is declared as "std_logic_vector", same type as LED. See line 42.
    LED <= std_logic_vector(count);     -- Typecasting: converts from "unsigned" to "std_logic_vector".
                                                -- This is always necessary when connecting signals and ports of different types.

-- Note: In order to run the simulation succesfully, you must comment lines 57, 58, and 63.
-- But it is important to leave those lines uncommented when implementing the desing.
end Behavioral;