library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.constants.all;

entity tb_top_level is
end entity tb_top_level;

architecture RTL of tb_top_level is
    constant period : time := 10 ns;
    signal clk : std_logic;
    signal rst : std_logic;
    signal ready: std_logic;
    signal cpu_rd: std_logic;
    signal cpu_wr: std_logic;
    signal dram_rd: std_logic;
    signal dram_wr: std_logic;
    signal done: std_logic;
    signal address: std_logic_vector(15 downto 0);
    signal data: std_logic_vector(15 downto 0);

begin
    ClockDriver : process
    begin
        clk <= '0';
        wait for period / 2;
        clk <= '1';
        wait for period / 2;
    end process ClockDriver;

    Cache: entity work.cache_controller
        port map(
            clk     => clk,
            rst     => rst,
            ready   => ready,
            cpu_rd  => cpu_rd,
            cpu_wr  => cpu_wr,
            dram_rd => dram_rd,
            dram_wr => dram_wr,
            done    => done,
            address => address,
            data    => data
        );

    Testbench : process
    begin
        -- read with miss
        cpu_rd  <= '1';
        cpu_wr  <= '0';
        done    <= '0';
        address <= "0000000000000000";
        data    <= "ZZZZZZZZZZZZZZZZ";
        wait for 100 ns;
        -- data read from dram simulation
        cpu_rd  <= '0';
        cpu_wr  <= '0';
        done    <= '1';
        address <= "0000000000000000";
        data    <= "0000000000000001";
        wait for 100 ns;
        -- read with miss
        cpu_rd  <= '1';
        cpu_wr  <= '0';
        done    <= '0';
        address <= "0000000000000001";
        data    <= "ZZZZZZZZZZZZZZZZ";
        wait for 100 ns;
        -- data read from dram simulation
        cpu_rd  <= '0';
        cpu_wr  <= '0';
        done    <= '1';
        address <= "0000000000000001";
        data    <= "0000000000000011";
        wait for 100 ns;
        -- read with hit
        cpu_rd  <= '1';
        cpu_wr  <= '0';
        done    <= '0';
        address <= "0000000000000000";
        wait for 100 ns;
        -- write with hit
        cpu_rd  <= '0';
        cpu_wr  <= '1';
        done    <= '0';
        address <= "0000000000000001";
        data    <= "0000000000000111";
        wait for 100 ns;
        -- write with miss
        cpu_rd  <= '0';
        cpu_wr  <= '1';
        done    <= '0';
        address <= "0000000000000010";
        data    <= "0000000000000111";
        wait for 100 ns;
    end process

end architecture RTL;