DEF FULLADDER
  PORT IN A
  PORT IN B
  PORT IN CIN
  PORT OUT S
  PORT OUT COUT

  NET ANANDB
  NET AXORB
  NET XOR1_NET1
  NET XOR1_NET2
  NET XOR2_NET1
  NET XOR2_NET2
  NET AXORB_NAND_CIN

  INST NAND1 NAND A B ANANDB
  INST NAND2 NAND A ANANDB XOR1_NET1
  INST NAND3 NAND B ANANDB XOR1_NET2
  INST NAND4 NAND XOR1_NET1 XOR1_NET2 AXORB
  INST NAND5 NAND AXORB CIN AXORB_NAND_CIN
  INST NAND6 NAND AXORB AXORB_NAND_CIN XOR2_NET1
  INST NAND7 NAND CIN AXORB_NAND_CIN XOR2_NET2
  INST NAND8 NAND XOR2_NET1 XOR2_NET2 S
  INST NAND9 NAND AXORB_NAND_CIN ANANDB COUT
ENDDEF

DEF ADDx8
  PORT IN A<7:0>
  PORT IN B<7:0>
  PORT IN CIN
  PORT OUT S<7:0>
  PORT OUT COUT

  NET COUT0
  NET COUT1
  NET COUT2
  NET COUT3
  NET COUT4
  NET COUT5
  NET COUT6

  INST FULLADDER0 FULLADDER A<0> B<0> CIN S<0> COUT0
  INST FULLADDER1 FULLADDER A<1> B<1> COUT0 S<1> COUT1
  INST FULLADDER2 FULLADDER A<2> B<2> COUT1 S<2> COUT2
  INST FULLADDER3 FULLADDER A<3> B<3> COUT2 S<3> COUT3
  INST FULLADDER4 FULLADDER A<4> B<4> COUT3 S<4> COUT4
  INST FULLADDER5 FULLADDER A<5> B<5> COUT4 S<5> COUT5
  INST FULLADDER6 FULLADDER A<6> B<6> COUT5 S<6> COUT6
  INST FULLADDER7 FULLADDER A<7> B<7> COUT6 S<7> COUT
ENDDEF