LIBRARY ieee;
USE ieee.std_logic_1164.ALL;



ENTITY test_circuito_combinado IS
END test_circuito_combinado;

ARCHITECTURE behavior OF test_circuito_combinado IS



    COMPONENT circuito_combinado
    PORT(
         EN : IN  std_logic_vector(0 to 9);
         ENA : IN  std_logic;
         DAT_B : IN  std_logic_vector(3 downto 0);
         EQU : OUT  std_logic;
         HIG : OUT  std_logic;
         LES : OUT  std_logic
        );
    END COMPONENT;



   --Inputs
   signal EN : std_logic_vector(0 to 9) := (others => '0');
   signal ENA : std_logic := '0';
   signal DAT_B : std_logic_vector(3 downto 0) := (others => '0');

 	--Outputs
   signal EQU : std_logic;
   signal HIG : std_logic;
   signal LES : std_logic;


BEGIN

	-- Instantiate the Unit Under Test (UUT)
   uut: circuito_combinado PORT MAP (
          EN => EN,
          ENA => ENA,
          DAT_B => DAT_B,
          EQU => EQU,
          HIG => HIG,
          LES => LES
        );


-- Valor de las CODIFICADOR
			ENA <='0' ,'1' AFTER 20 ns , '0' AFTER 120 ns , '1' after 140 ns , '0' AFTER 300 ns;
			EN <="0000000000" , "1000000000" AFTER 40 ns , "1111111111" AFTER 80 ns, "1100000000" AFTER 100 ns , "1111111110" AFTER 140 ns ,
			"1111111000" AFTER 160 ns , "1110011011" AFTER 200 ns ,"1000000000" AFTER  240 ns , "1111111111" AFTER 280 ns;
--Valor de las señales COMPARADOR

			DAT_B <= "0000","0110" after 40 ns,"1000" after 80 ns,"0000" after 120 ns, "1101" after 160 ns,"0111" after 200 ns;




END;