testripplecarry

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;

ENTITY testripple IS
END testripple;

ARCHITECTURE behavior OF testripple IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT ripplecarry
    PORT(
         a : IN  std_logic_vector(3 downto 0);
         b : IN  std_logic_vector(3 downto 0);
         cin : IN  std_logic;
         c : OUT  std_logic_vector(3 downto 0);
         cout : OUT  std_logic
        );
    END COMPONENT;


   --Inputs
   signal a : std_logic_vector(3 downto 0) := (others => '0');
   signal b : std_logic_vector(3 downto 0) := (others => '0');
   signal cin : std_logic := '0';

    --Outputs
   signal c : std_logic_vector(3 downto 0);
   signal cout : std_logic;
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: ripplecarry PORT MAP (
          a => a,
          b => b,
          cin => cin,
          c => c,
          cout => cout
        );

   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
      wait for 100 ns;

      -- insert stimulus here
        cin <= '0';
        a   <= "0001";
        b   <= "0010";
      wait for 100 ns;

        cin <= '0';
        a   <= "0011";
        b   <= "0100";
      wait for 100 ns;

        cin <= '0';
        a   <= "0101";
        b   <= "0110";
      wait for 100 ns;

        cin <= '0';
        a   <= "0111";
        b   <= "1000";
      wait for 100 ns;

        cin <= '1';
        a   <= "0001";
        b   <= "0010";
      wait for 100 ns;

        cin <= '1';
        a   <= "0011";
        b   <= "0100";
      wait for 100 ns;

        cin <= '1';
        a   <= "0101";
        b   <= "0110";
      wait for 100 ns;

        cin <= '1';
        a   <= "0111";
        b   <= "1000";
      wait for 100 ns;

      wait;
   end process;

END;