LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY count9 IS
PORT (CLK_50MHZ, reset, key1: IN std_logic;  -- reset, key1 and key2 are inputs
       clk : OUT std_logic);                        -- clk is final output signal, CLK_1HZ is referenced to it
END count9;

ARCHITECTURE behav OF count9 IS

SIGNAL CLK_COUNT_1HZ: STD_LOGIC_VECTOR(24 DOWNTO 0);  --needed space for binary of 500000000
SIGNAL  CLK_1HZ: STD_LOGIC; -- final result signal of 1 second
SIGNAl counter: INTEGER:=0; -- counter neeeded to count desired number of cycles, initially Zero


BEGIN
   PROCESS (CLK_50MHZ, reset)
      BEGIN
        IF reset = '1' THEN
		  counter<=0;
        CLK_COUNT_1HZ <= "0000000000000000000000000";   --total 25 spaces for binary bit of 50M, zero as default
        CLK_1HZ <= '0';                                 --initially set to zero
        ELSIF rising_edge(CLK_50MHZ) THEN




		  IF reset = '0' THEN
          IF CLK_COUNT_1HZ < X"17D7840" THEN            --17D7840 is hex of 50M
          CLK_COUNT_1HZ <= CLK_COUNT_1HZ + 1;           --checks 1 second counts up after each 1 second.
          ELSE
          CLK_COUNT_1HZ <= "0000000000000000000000000";
			    IF counter < 9 THEN                        -- Condition to check is 9 seconds or 9 signals have passed
			      counter<=counter+1;
			    ELSE
			      CLK_1HZ <= '1';
		       END IF;
		    END IF;

		 IF key1 = '0' THEN
          IF CLK_COUNT_1HZ < X"17D7840" THEN            --17D7840 is hex of 50M
          CLK_COUNT_1HZ <= CLK_COUNT_1HZ + 1;           --checks 1 second counts up after each 1 second.
          ELSE
          CLK_COUNT_1HZ <= "0000000000000000000000000";
			    IF counter < 9 THEN                        -- Condition to check is 9 seconds or 9 signals have passed
			      counter<=counter+1;
			    ELSE
			      CLK_1HZ <= '1';
		       END IF;
		    END IF;

         END IF;
         clk<=CLK_1HZ;                                  -- CLK_1HZ is now clk
   END PROCESS;
 END behav;