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  1. /dts-v1/;
  2. // magic: 0xd00dfeed
  3. // totalsize: 0x10f87 (69511)
  4. // off_dt_struct: 0x98
  5. // off_dt_strings: 0xea30
  6. // off_mem_rsvmap: 0x28
  7. // version: 17
  8. // last_comp_version: 16
  9. // boot_cpuid_phys: 0x0
  10. // size_dt_strings: 0x2557
  11. // size_dt_struct: 0xe998
  12.  
  13. /memreserve/ 0x45000000 0x200000;
  14. /memreserve/ 0x41010000 0x10000;
  15. /memreserve/ 0x41020000 0x800;
  16. /memreserve/ 0x40100000 0x4000;
  17. /memreserve/ 0x40104000 0x1000;
  18. /memreserve/ 0x40105000 0x1000;
  19. / {
  20. model = "sun50iw1p1";
  21. compatible = "arm,sun50iw1p1", "arm,sun50iw1p1";
  22. interrupt-parent = <0x00000001>;
  23. #address-cells = <0x00000002>;
  24. #size-cells = <0x00000002>;
  25. clocks {
  26. compatible = "allwinner,sunxi-clk-init";
  27. device_type = "clocks";
  28. #address-cells = <0x00000002>;
  29. #size-cells = <0x00000002>;
  30. ranges;
  31. reg = <0x00000000 0x01c20000 0x00000000 0x00000320 0x00000000 0x01f01400 0x00000000 0x000000b0 0x00000000 0x01f00060 0x00000000 0x00000004>;
  32. losc {
  33. #clock-cells = <0x00000000>;
  34. compatible = "allwinner,fixed-clock";
  35. clock-frequency = <0x00008000>;
  36. clock-output-names = "losc";
  37. linux,phandle = <0x0000000c>;
  38. phandle = <0x0000000c>;
  39. };
  40. iosc {
  41. #clock-cells = <0x00000000>;
  42. compatible = "allwinner,fixed-clock";
  43. clock-frequency = <0x00f42400>;
  44. clock-output-names = "iosc";
  45. linux,phandle = <0x0000000d>;
  46. phandle = <0x0000000d>;
  47. };
  48. hosc {
  49. #clock-cells = <0x00000000>;
  50. compatible = "allwinner,fixed-clock";
  51. clock-frequency = <0x016e3600>;
  52. clock-output-names = "hosc";
  53. linux,phandle = <0x00000006>;
  54. phandle = <0x00000006>;
  55. };
  56. pll_cpu {
  57. #clock-cells = <0x00000000>;
  58. compatible = "allwinner,sunxi-pll-clock";
  59. lock-mode = "new";
  60. clock-output-names = "pll_cpu";
  61. };
  62. pll_audio {
  63. #clock-cells = <0x00000000>;
  64. compatible = "allwinner,sunxi-pll-clock";
  65. lock-mode = "new";
  66. assigned-clock-rates = <0x01770000>;
  67. clock-output-names = "pll_audio";
  68. linux,phandle = <0x00000002>;
  69. phandle = <0x00000002>;
  70. };
  71. pll_video0 {
  72. #clock-cells = <0x00000000>;
  73. compatible = "allwinner,sunxi-pll-clock";
  74. lock-mode = "new";
  75. assigned-clock-rates = <0x11b3dc40>;
  76. clock-output-names = "pll_video0";
  77. linux,phandle = <0x00000003>;
  78. phandle = <0x00000003>;
  79. };
  80. pll_ve {
  81. #clock-cells = <0x00000000>;
  82. compatible = "allwinner,sunxi-pll-clock";
  83. lock-mode = "new";
  84. clock-output-names = "pll_ve";
  85. linux,phandle = <0x00000016>;
  86. phandle = <0x00000016>;
  87. };
  88. pll_ddr0 {
  89. #clock-cells = <0x00000000>;
  90. compatible = "allwinner,sunxi-pll-clock";
  91. lock-mode = "new";
  92. clock-output-names = "pll_ddr0";
  93. linux,phandle = <0x00000093>;
  94. phandle = <0x00000093>;
  95. };
  96. pll_periph0 {
  97. #clock-cells = <0x00000000>;
  98. compatible = "allwinner,sunxi-pll-clock";
  99. lock-mode = "new";
  100. clock-output-names = "pll_periph0";
  101. linux,phandle = <0x00000004>;
  102. phandle = <0x00000004>;
  103. };
  104. pll_periph1 {
  105. #clock-cells = <0x00000000>;
  106. compatible = "allwinner,sunxi-pll-clock";
  107. lock-mode = "new";
  108. clock-output-names = "pll_periph1";
  109. linux,phandle = <0x00000005>;
  110. phandle = <0x00000005>;
  111. };
  112. pll_video1 {
  113. #clock-cells = <0x00000000>;
  114. compatible = "allwinner,sunxi-pll-clock";
  115. lock-mode = "new";
  116. assigned-clock-rates = <0x11b3dc40>;
  117. clock-output-names = "pll_video1";
  118. };
  119. pll_gpu {
  120. #clock-cells = <0x00000000>;
  121. compatible = "allwinner,sunxi-pll-clock";
  122. lock-mode = "new";
  123. clock-output-names = "pll_gpu";
  124. linux,phandle = <0x00000096>;
  125. phandle = <0x00000096>;
  126. };
  127. pll_mipi {
  128. #clock-cells = <0x00000000>;
  129. compatible = "allwinner,sunxi-pll-clock";
  130. lock-mode = "new";
  131. clock-output-names = "pll_mipi";
  132. linux,phandle = <0x00000008>;
  133. phandle = <0x00000008>;
  134. };
  135. pll_hsic {
  136. #clock-cells = <0x00000000>;
  137. compatible = "allwinner,sunxi-pll-clock";
  138. lock-mode = "new";
  139. clock-output-names = "pll_hsic";
  140. linux,phandle = <0x0000003a>;
  141. phandle = <0x0000003a>;
  142. };
  143. pll_de {
  144. #clock-cells = <0x00000000>;
  145. compatible = "allwinner,sunxi-pll-clock";
  146. lock-mode = "new";
  147. assigned-clock-rates = <0x11b3dc40>;
  148. clock-output-names = "pll_de";
  149. linux,phandle = <0x00000007>;
  150. phandle = <0x00000007>;
  151. };
  152. pll_ddr1 {
  153. #clock-cells = <0x00000000>;
  154. compatible = "allwinner,sunxi-pll-clock";
  155. lock-mode = "new";
  156. clock-output-names = "pll_ddr1";
  157. linux,phandle = <0x00000094>;
  158. phandle = <0x00000094>;
  159. };
  160. pll_audiox8 {
  161. #clock-cells = <0x00000000>;
  162. compatible = "allwinner,fixed-factor-clock";
  163. clocks = <0x00000002>;
  164. clock-mult = <0x00000008>;
  165. clock-div = <0x00000001>;
  166. clock-output-names = "pll_audiox8";
  167. };
  168. pll_audiox4 {
  169. #clock-cells = <0x00000000>;
  170. compatible = "allwinner,fixed-factor-clock";
  171. clocks = <0x00000002>;
  172. clock-mult = <0x00000008>;
  173. clock-div = <0x00000002>;
  174. clock-output-names = "pll_audiox4";
  175. linux,phandle = <0x0000003c>;
  176. phandle = <0x0000003c>;
  177. };
  178. pll_audiox2 {
  179. #clock-cells = <0x00000000>;
  180. compatible = "allwinner,fixed-factor-clock";
  181. clocks = <0x00000002>;
  182. clock-mult = <0x00000008>;
  183. clock-div = <0x00000004>;
  184. clock-output-names = "pll_audiox2";
  185. };
  186. pll_video0x2 {
  187. #clock-cells = <0x00000000>;
  188. compatible = "allwinner,fixed-factor-clock";
  189. clocks = <0x00000003>;
  190. clock-mult = <0x00000002>;
  191. clock-div = <0x00000001>;
  192. clock-output-names = "pll_video0x2";
  193. };
  194. pll_periph0x2 {
  195. #clock-cells = <0x00000000>;
  196. compatible = "allwinner,fixed-factor-clock";
  197. clocks = <0x00000004>;
  198. clock-mult = <0x00000002>;
  199. clock-div = <0x00000001>;
  200. clock-output-names = "pll_periph0x2";
  201. linux,phandle = <0x0000007b>;
  202. phandle = <0x0000007b>;
  203. };
  204. pll_periph1x2 {
  205. #clock-cells = <0x00000000>;
  206. compatible = "allwinner,fixed-factor-clock";
  207. clocks = <0x00000005>;
  208. clock-mult = <0x00000002>;
  209. clock-div = <0x00000001>;
  210. clock-output-names = "pll_periph1x2";
  211. linux,phandle = <0x0000005a>;
  212. phandle = <0x0000005a>;
  213. };
  214. pll_periph0d2 {
  215. #clock-cells = <0x00000000>;
  216. compatible = "allwinner,fixed-factor-clock";
  217. clocks = <0x00000004>;
  218. clock-mult = <0x00000001>;
  219. clock-div = <0x00000002>;
  220. clock-output-names = "pll_periph0d2";
  221. };
  222. hoscd2 {
  223. #clock-cells = <0x00000000>;
  224. compatible = "allwinner,fixed-factor-clock";
  225. clocks = <0x00000006>;
  226. clock-mult = <0x00000001>;
  227. clock-div = <0x00000002>;
  228. clock-output-names = "hoscd2";
  229. };
  230. cpu {
  231. #clock-cells = <0x00000000>;
  232. compatible = "allwinner,sunxi-periph-clock";
  233. clock-output-names = "cpu";
  234. };
  235. cpuapb {
  236. #clock-cells = <0x00000000>;
  237. compatible = "allwinner,sunxi-periph-clock";
  238. clock-output-names = "cpuapb";
  239. };
  240. axi {
  241. #clock-cells = <0x00000000>;
  242. compatible = "allwinner,sunxi-periph-clock";
  243. clock-output-names = "axi";
  244. };
  245. pll_periphahb0 {
  246. #clock-cells = <0x00000000>;
  247. compatible = "allwinner,sunxi-periph-clock";
  248. clock-output-names = "pll_periphahb0";
  249. };
  250. ahb1 {
  251. #clock-cells = <0x00000000>;
  252. compatible = "allwinner,sunxi-periph-clock";
  253. clock-output-names = "ahb1";
  254. linux,phandle = <0x00000095>;
  255. phandle = <0x00000095>;
  256. };
  257. apb1 {
  258. #clock-cells = <0x00000000>;
  259. compatible = "allwinner,sunxi-periph-clock";
  260. clock-output-names = "apb1";
  261. };
  262. apb2 {
  263. #clock-cells = <0x00000000>;
  264. compatible = "allwinner,sunxi-periph-clock";
  265. clock-output-names = "apb2";
  266. linux,phandle = <0x0000007e>;
  267. phandle = <0x0000007e>;
  268. };
  269. ahb2 {
  270. #clock-cells = <0x00000000>;
  271. compatible = "allwinner,sunxi-periph-clock";
  272. clock-output-names = "ahb2";
  273. };
  274. ths {
  275. #clock-cells = <0x00000000>;
  276. compatible = "allwinner,sunxi-periph-clock";
  277. clock-output-names = "ths";
  278. linux,phandle = <0x00000084>;
  279. phandle = <0x00000084>;
  280. };
  281. nand {
  282. #clock-cells = <0x00000000>;
  283. compatible = "allwinner,sunxi-periph-clock";
  284. clock-output-names = "nand";
  285. linux,phandle = <0x00000080>;
  286. phandle = <0x00000080>;
  287. };
  288. sdmmc0_mod {
  289. #clock-cells = <0x00000000>;
  290. compatible = "allwinner,sunxi-periph-clock";
  291. clock-output-names = "sdmmc0_mod";
  292. linux,phandle = <0x00000060>;
  293. phandle = <0x00000060>;
  294. };
  295. sdmmc0_bus {
  296. #clock-cells = <0x00000000>;
  297. compatible = "allwinner,sunxi-periph-clock";
  298. clock-output-names = "sdmmc0_bus";
  299. linux,phandle = <0x00000061>;
  300. phandle = <0x00000061>;
  301. };
  302. sdmmc0_rst {
  303. #clock-cells = <0x00000000>;
  304. compatible = "allwinner,sunxi-periph-clock";
  305. clock-output-names = "sdmmc0_rst";
  306. linux,phandle = <0x00000062>;
  307. phandle = <0x00000062>;
  308. };
  309. sdmmc1_mod {
  310. #clock-cells = <0x00000000>;
  311. compatible = "allwinner,sunxi-periph-clock";
  312. clock-output-names = "sdmmc1_mod";
  313. linux,phandle = <0x00000065>;
  314. phandle = <0x00000065>;
  315. };
  316. sdmmc1_bus {
  317. #clock-cells = <0x00000000>;
  318. compatible = "allwinner,sunxi-periph-clock";
  319. clock-output-names = "sdmmc1_bus";
  320. linux,phandle = <0x00000066>;
  321. phandle = <0x00000066>;
  322. };
  323. sdmmc1_rst {
  324. #clock-cells = <0x00000000>;
  325. compatible = "allwinner,sunxi-periph-clock";
  326. clock-output-names = "sdmmc1_rst";
  327. linux,phandle = <0x00000067>;
  328. phandle = <0x00000067>;
  329. };
  330. sdmmc2_mod {
  331. #clock-cells = <0x00000000>;
  332. compatible = "allwinner,sunxi-periph-clock";
  333. clock-output-names = "sdmmc2_mod";
  334. linux,phandle = <0x0000005b>;
  335. phandle = <0x0000005b>;
  336. };
  337. sdmmc2_bus {
  338. #clock-cells = <0x00000000>;
  339. compatible = "allwinner,sunxi-periph-clock";
  340. clock-output-names = "sdmmc2_bus";
  341. linux,phandle = <0x0000005c>;
  342. phandle = <0x0000005c>;
  343. };
  344. sdmmc2_rst {
  345. #clock-cells = <0x00000000>;
  346. compatible = "allwinner,sunxi-periph-clock";
  347. clock-output-names = "sdmmc2_rst";
  348. linux,phandle = <0x0000005d>;
  349. phandle = <0x0000005d>;
  350. };
  351. ts {
  352. #clock-cells = <0x00000000>;
  353. compatible = "allwinner,sunxi-periph-clock";
  354. clock-output-names = "ts";
  355. };
  356. ce {
  357. #clock-cells = <0x00000000>;
  358. compatible = "allwinner,sunxi-periph-clock";
  359. clock-output-names = "ce";
  360. linux,phandle = <0x0000007a>;
  361. phandle = <0x0000007a>;
  362. };
  363. spi0 {
  364. #clock-cells = <0x00000000>;
  365. compatible = "allwinner,sunxi-periph-clock";
  366. clock-output-names = "spi0";
  367. linux,phandle = <0x00000052>;
  368. phandle = <0x00000052>;
  369. };
  370. spi1 {
  371. #clock-cells = <0x00000000>;
  372. compatible = "allwinner,sunxi-periph-clock";
  373. clock-output-names = "spi1";
  374. linux,phandle = <0x00000056>;
  375. phandle = <0x00000056>;
  376. };
  377. i2s0 {
  378. #clock-cells = <0x00000000>;
  379. compatible = "allwinner,sunxi-periph-clock";
  380. clock-output-names = "i2s0";
  381. linux,phandle = <0x00000042>;
  382. phandle = <0x00000042>;
  383. };
  384. i2s1 {
  385. #clock-cells = <0x00000000>;
  386. compatible = "allwinner,sunxi-periph-clock";
  387. clock-output-names = "i2s1";
  388. linux,phandle = <0x00000047>;
  389. phandle = <0x00000047>;
  390. };
  391. i2s2 {
  392. #clock-cells = <0x00000000>;
  393. compatible = "allwinner,sunxi-periph-clock";
  394. clock-output-names = "i2s2";
  395. linux,phandle = <0x00000048>;
  396. phandle = <0x00000048>;
  397. };
  398. spdif {
  399. #clock-cells = <0x00000000>;
  400. compatible = "allwinner,sunxi-periph-clock";
  401. clock-output-names = "spdif";
  402. linux,phandle = <0x00000049>;
  403. phandle = <0x00000049>;
  404. };
  405. usbphy0 {
  406. #clock-cells = <0x00000000>;
  407. compatible = "allwinner,sunxi-periph-clock";
  408. clock-output-names = "usbphy0";
  409. linux,phandle = <0x00000032>;
  410. phandle = <0x00000032>;
  411. };
  412. usbphy1 {
  413. #clock-cells = <0x00000000>;
  414. compatible = "allwinner,sunxi-periph-clock";
  415. clock-output-names = "usbphy1";
  416. linux,phandle = <0x00000036>;
  417. phandle = <0x00000036>;
  418. };
  419. usbhsic {
  420. #clock-cells = <0x00000000>;
  421. compatible = "allwinner,sunxi-periph-clock";
  422. clock-output-names = "usbhsic";
  423. linux,phandle = <0x00000038>;
  424. phandle = <0x00000038>;
  425. };
  426. usbhsic12m {
  427. #clock-cells = <0x00000000>;
  428. compatible = "allwinner,sunxi-periph-clock";
  429. clock-output-names = "usbhsic12m";
  430. linux,phandle = <0x00000039>;
  431. phandle = <0x00000039>;
  432. };
  433. usbohci1 {
  434. #clock-cells = <0x00000000>;
  435. compatible = "allwinner,sunxi-periph-clock";
  436. clock-output-names = "usbohci1";
  437. linux,phandle = <0x0000003b>;
  438. phandle = <0x0000003b>;
  439. };
  440. usbohci0 {
  441. #clock-cells = <0x00000000>;
  442. compatible = "allwinner,sunxi-periph-clock";
  443. clock-output-names = "usbohci0";
  444. linux,phandle = <0x00000035>;
  445. phandle = <0x00000035>;
  446. };
  447. de {
  448. #clock-cells = <0x00000000>;
  449. compatible = "allwinner,sunxi-periph-clock";
  450. assigned-clock-parents = <0x00000007>;
  451. assigned-clock-rates = <0x11b3dc40>;
  452. clock-output-names = "de";
  453. linux,phandle = <0x0000006a>;
  454. phandle = <0x0000006a>;
  455. };
  456. tcon0 {
  457. #clock-cells = <0x00000000>;
  458. compatible = "allwinner,sunxi-periph-clock";
  459. assigned-clock-parents = <0x00000008>;
  460. clock-output-names = "tcon0";
  461. linux,phandle = <0x0000006b>;
  462. phandle = <0x0000006b>;
  463. };
  464. tcon1 {
  465. #clock-cells = <0x00000000>;
  466. compatible = "allwinner,sunxi-periph-clock";
  467. assigned-clock-parents = <0x00000003>;
  468. clock-output-names = "tcon1";
  469. linux,phandle = <0x0000006e>;
  470. phandle = <0x0000006e>;
  471. };
  472. deinterlace {
  473. #clock-cells = <0x00000000>;
  474. compatible = "allwinner,sunxi-periph-clock";
  475. clock-output-names = "deinterlace";
  476. linux,phandle = <0x0000007c>;
  477. phandle = <0x0000007c>;
  478. };
  479. csi_s {
  480. #clock-cells = <0x00000000>;
  481. compatible = "allwinner,sunxi-periph-clock";
  482. clock-output-names = "csi_s";
  483. linux,phandle = <0x00000073>;
  484. phandle = <0x00000073>;
  485. };
  486. csi_m {
  487. #clock-cells = <0x00000000>;
  488. compatible = "allwinner,sunxi-periph-clock";
  489. clock-output-names = "csi_m";
  490. linux,phandle = <0x00000074>;
  491. phandle = <0x00000074>;
  492. };
  493. csi_misc {
  494. #clock-cells = <0x00000000>;
  495. compatible = "allwinner,sunxi-periph-clock";
  496. clock-output-names = "csi_misc";
  497. linux,phandle = <0x00000075>;
  498. phandle = <0x00000075>;
  499. };
  500. ve {
  501. #clock-cells = <0x00000000>;
  502. compatible = "allwinner,sunxi-periph-clock";
  503. clock-output-names = "ve";
  504. linux,phandle = <0x00000017>;
  505. phandle = <0x00000017>;
  506. };
  507. adda {
  508. #clock-cells = <0x00000000>;
  509. compatible = "allwinner,sunxi-periph-clock";
  510. clock-output-names = "adda";
  511. linux,phandle = <0x00000041>;
  512. phandle = <0x00000041>;
  513. };
  514. addax4 {
  515. #clock-cells = <0x00000000>;
  516. compatible = "allwinner,sunxi-periph-clock";
  517. clock-output-names = "addax4";
  518. };
  519. avs {
  520. #clock-cells = <0x00000000>;
  521. compatible = "allwinner,sunxi-periph-clock";
  522. clock-output-names = "avs";
  523. };
  524. hdmi {
  525. #clock-cells = <0x00000000>;
  526. compatible = "allwinner,sunxi-periph-clock";
  527. assigned-clock-parents = <0x00000003>;
  528. clock-output-names = "hdmi";
  529. linux,phandle = <0x0000006f>;
  530. phandle = <0x0000006f>;
  531. };
  532. hdmi_slow {
  533. #clock-cells = <0x00000000>;
  534. compatible = "allwinner,sunxi-periph-clock";
  535. clock-output-names = "hdmi_slow";
  536. linux,phandle = <0x00000070>;
  537. phandle = <0x00000070>;
  538. };
  539. mbus {
  540. #clock-cells = <0x00000000>;
  541. compatible = "allwinner,sunxi-periph-clock";
  542. clock-output-names = "mbus";
  543. };
  544. mipidsi {
  545. #clock-cells = <0x00000000>;
  546. compatible = "allwinner,sunxi-periph-clock";
  547. clock-output-names = "mipidsi";
  548. linux,phandle = <0x0000006d>;
  549. phandle = <0x0000006d>;
  550. };
  551. gpu {
  552. #clock-cells = <0x00000000>;
  553. compatible = "allwinner,sunxi-periph-clock";
  554. clock-output-names = "gpu";
  555. linux,phandle = <0x00000097>;
  556. phandle = <0x00000097>;
  557. };
  558. usbehci_16 {
  559. #clock-cells = <0x00000000>;
  560. compatible = "allwinner,sunxi-periph-clock";
  561. clock-output-names = "usbohci_16";
  562. };
  563. usbehci1 {
  564. #clock-cells = <0x00000000>;
  565. compatible = "allwinner,sunxi-periph-clock";
  566. clock-output-names = "usbehci1";
  567. linux,phandle = <0x00000037>;
  568. phandle = <0x00000037>;
  569. };
  570. usbehci0 {
  571. #clock-cells = <0x00000000>;
  572. compatible = "allwinner,sunxi-periph-clock";
  573. clock-output-names = "usbehci0";
  574. linux,phandle = <0x00000034>;
  575. phandle = <0x00000034>;
  576. };
  577. usbotg {
  578. #clock-cells = <0x00000000>;
  579. compatible = "allwinner,sunxi-periph-clock";
  580. clock-output-names = "usbotg";
  581. linux,phandle = <0x00000033>;
  582. phandle = <0x00000033>;
  583. };
  584. gmac {
  585. #clock-cells = <0x00000000>;
  586. compatible = "allwinner,sunxi-periph-clock";
  587. clock-output-names = "gmac";
  588. linux,phandle = <0x0000008f>;
  589. phandle = <0x0000008f>;
  590. };
  591. sdram {
  592. #clock-cells = <0x00000000>;
  593. compatible = "allwinner,sunxi-periph-clock";
  594. clock-output-names = "sdram";
  595. };
  596. dma {
  597. #clock-cells = <0x00000000>;
  598. compatible = "allwinner,sunxi-periph-clock";
  599. clock-output-names = "dma";
  600. linux,phandle = <0x0000000b>;
  601. phandle = <0x0000000b>;
  602. };
  603. hwspinlock_rst {
  604. #clock-cells = <0x00000000>;
  605. compatible = "allwinner,sunxi-periph-clock";
  606. clock-output-names = "hwspinlock_rst";
  607. linux,phandle = <0x0000000f>;
  608. phandle = <0x0000000f>;
  609. };
  610. hwspinlock_bus {
  611. #clock-cells = <0x00000000>;
  612. compatible = "allwinner,sunxi-periph-clock";
  613. clock-output-names = "hwspinlock_bus";
  614. linux,phandle = <0x00000010>;
  615. phandle = <0x00000010>;
  616. };
  617. msgbox {
  618. #clock-cells = <0x00000000>;
  619. compatible = "allwinner,sunxi-periph-clock";
  620. clock-output-names = "msgbox";
  621. linux,phandle = <0x0000000e>;
  622. phandle = <0x0000000e>;
  623. };
  624. lvds {
  625. #clock-cells = <0x00000000>;
  626. compatible = "allwinner,sunxi-periph-clock";
  627. clock-output-names = "lvds";
  628. linux,phandle = <0x0000006c>;
  629. phandle = <0x0000006c>;
  630. };
  631. uart0 {
  632. #clock-cells = <0x00000000>;
  633. compatible = "allwinner,sunxi-periph-clock";
  634. clock-output-names = "uart0";
  635. linux,phandle = <0x00000018>;
  636. phandle = <0x00000018>;
  637. };
  638. uart1 {
  639. #clock-cells = <0x00000000>;
  640. compatible = "allwinner,sunxi-periph-clock";
  641. clock-output-names = "uart1";
  642. linux,phandle = <0x0000001b>;
  643. phandle = <0x0000001b>;
  644. };
  645. uart2 {
  646. #clock-cells = <0x00000000>;
  647. compatible = "allwinner,sunxi-periph-clock";
  648. clock-output-names = "uart2";
  649. linux,phandle = <0x0000001e>;
  650. phandle = <0x0000001e>;
  651. };
  652. uart3 {
  653. #clock-cells = <0x00000000>;
  654. compatible = "allwinner,sunxi-periph-clock";
  655. clock-output-names = "uart3";
  656. linux,phandle = <0x00000021>;
  657. phandle = <0x00000021>;
  658. };
  659. uart4 {
  660. #clock-cells = <0x00000000>;
  661. compatible = "allwinner,sunxi-periph-clock";
  662. clock-output-names = "uart4";
  663. linux,phandle = <0x00000024>;
  664. phandle = <0x00000024>;
  665. };
  666. scr {
  667. #clock-cells = <0x00000000>;
  668. compatible = "allwinner,sunxi-periph-clock";
  669. clock-output-names = "scr";
  670. linux,phandle = <0x0000007d>;
  671. phandle = <0x0000007d>;
  672. };
  673. twi0 {
  674. #clock-cells = <0x00000000>;
  675. compatible = "allwinner,sunxi-periph-clock";
  676. clock-output-names = "twi0";
  677. linux,phandle = <0x00000027>;
  678. phandle = <0x00000027>;
  679. };
  680. twi1 {
  681. #clock-cells = <0x00000000>;
  682. compatible = "allwinner,sunxi-periph-clock";
  683. clock-output-names = "twi1";
  684. linux,phandle = <0x0000002a>;
  685. phandle = <0x0000002a>;
  686. };
  687. twi2 {
  688. #clock-cells = <0x00000000>;
  689. compatible = "allwinner,sunxi-periph-clock";
  690. clock-output-names = "twi2";
  691. linux,phandle = <0x0000002d>;
  692. phandle = <0x0000002d>;
  693. };
  694. twi3 {
  695. #clock-cells = <0x00000000>;
  696. compatible = "allwinner,sunxi-periph-clock";
  697. clock-output-names = "twi3";
  698. };
  699. pio {
  700. #clock-cells = <0x00000000>;
  701. compatible = "allwinner,sunxi-periph-clock";
  702. clock-output-names = "pio";
  703. linux,phandle = <0x0000000a>;
  704. phandle = <0x0000000a>;
  705. };
  706. cpurcir {
  707. #clock-cells = <0x00000000>;
  708. compatible = "allwinner,sunxi-periph-cpus-clock";
  709. clock-output-names = "cpurcir";
  710. linux,phandle = <0x00000012>;
  711. phandle = <0x00000012>;
  712. };
  713. cpurpio {
  714. #clock-cells = <0x00000000>;
  715. compatible = "allwinner,sunxi-periph-cpus-clock";
  716. clock-output-names = "cpurpio";
  717. linux,phandle = <0x00000009>;
  718. phandle = <0x00000009>;
  719. };
  720. cpurpll_peri0 {
  721. #clock-cells = <0x00000000>;
  722. compatible = "allwinner,sunxi-periph-cpus-clock";
  723. clock-output-names = "cpurpll_peri0";
  724. };
  725. cpurcpus {
  726. #clock-cells = <0x00000000>;
  727. compatible = "allwinner,sunxi-periph-cpus-clock";
  728. clock-output-names = "cpurcpus";
  729. };
  730. cpurahbs {
  731. #clock-cells = <0x00000000>;
  732. compatible = "allwinner,sunxi-periph-cpus-clock";
  733. clock-output-names = "cpurahbs";
  734. };
  735. cpurapbs {
  736. #clock-cells = <0x00000000>;
  737. compatible = "allwinner,sunxi-periph-cpus-clock";
  738. clock-output-names = "cpurapbs";
  739. };
  740. losc_out {
  741. #clock-cells = <0x00000000>;
  742. compatible = "allwinner,sunxi-periph-cpus-clock";
  743. clock-output-names = "losc_out";
  744. linux,phandle = <0x00000098>;
  745. phandle = <0x00000098>;
  746. };
  747. };
  748. soc@01c00000 {
  749. compatible = "simple-bus";
  750. #address-cells = <0x00000002>;
  751. #size-cells = <0x00000002>;
  752. ranges;
  753. device_type = "soc";
  754. pinctrl@01f02c00 {
  755. compatible = "allwinner,sun50i-r-pinctrl";
  756. reg = <0x00000000 0x01f02c00 0x00000000 0x00000400>;
  757. interrupts = <0x00000000 0x0000002d 0x00000004>;
  758. clocks = <0x00000009>;
  759. device_type = "r_pio";
  760. gpio-controller;
  761. interrupt-controller;
  762. #interrupt-cells = <0x00000002>;
  763. #size-cells = <0x00000000>;
  764. #gpio-cells = <0x00000006>;
  765. linux,phandle = <0x00000079>;
  766. phandle = <0x00000079>;
  767. s_cir0@0 {
  768. allwinner,pins = "PL11";
  769. allwinner,function = "s_cir0";
  770. allwinner,muxsel = <0x00000002>;
  771. allwinner,drive = <0x00000002>;
  772. allwinner,pull = <0x00000001>;
  773. linux,phandle = <0x00000011>;
  774. phandle = <0x00000011>;
  775. };
  776. spwm0@0 {
  777. linux,phandle = <0x000000af>;
  778. phandle = <0x000000af>;
  779. allwinner,pins = "PL10";
  780. allwinner,function = "spwm0";
  781. allwinner,pname = "pwm_positive";
  782. allwinner,muxsel = <0x00000002>;
  783. allwinner,pull = <0x00000000>;
  784. allwinner,drive = <0xffffffff>;
  785. allwinner,data = <0xffffffff>;
  786. };
  787. spwm0@1 {
  788. linux,phandle = <0x000000b0>;
  789. phandle = <0x000000b0>;
  790. allwinner,pins = "PL10";
  791. allwinner,function = "spwm0";
  792. allwinner,pname = "pwm_positive";
  793. allwinner,muxsel = <0x00000007>;
  794. allwinner,pull = <0x00000000>;
  795. allwinner,drive = <0xffffffff>;
  796. allwinner,data = <0xffffffff>;
  797. };
  798. s_uart0@0 {
  799. linux,phandle = <0x000000b6>;
  800. phandle = <0x000000b6>;
  801. allwinner,pins = "PL2", "PL3";
  802. allwinner,function = "s_uart0";
  803. allwinner,pname = "s_uart0_tx", "s_uart0_rx";
  804. allwinner,muxsel = <0x00000002>;
  805. allwinner,pull = <0xffffffff>;
  806. allwinner,drive = <0xffffffff>;
  807. allwinner,data = <0xffffffff>;
  808. };
  809. s_rsb0@0 {
  810. linux,phandle = <0x000000b7>;
  811. phandle = <0x000000b7>;
  812. allwinner,pins = "PL0", "PL1";
  813. allwinner,function = "s_rsb0";
  814. allwinner,pname = "s_rsb0_sck", "s_rsb0_sda";
  815. allwinner,muxsel = <0x00000002>;
  816. allwinner,pull = <0x00000001>;
  817. allwinner,drive = <0x00000002>;
  818. allwinner,data = <0xffffffff>;
  819. };
  820. s_jtag0@0 {
  821. linux,phandle = <0x000000b8>;
  822. phandle = <0x000000b8>;
  823. allwinner,pins = "PL4", "PL5", "PL6", "PL7";
  824. allwinner,function = "s_jtag0";
  825. allwinner,pname = "s_jtag0_tms", "s_jtag0_tck", "s_jtag0_tdo", "s_jtag0_tdi";
  826. allwinner,muxsel = <0x00000002>;
  827. allwinner,pull = <0x00000001>;
  828. allwinner,drive = <0x00000002>;
  829. allwinner,data = <0xffffffff>;
  830. };
  831. };
  832. pinctrl@01c20800 {
  833. compatible = "allwinner,sun50i-pinctrl";
  834. reg = <0x00000000 0x01c20800 0x00000000 0x00000400>;
  835. interrupts = <0x00000000 0x0000000b 0x00000004 0x00000000 0x00000011 0x00000004 0x00000000 0x00000015 0x00000004>;
  836. device_type = "pio";
  837. clocks = <0x0000000a>;
  838. gpio-controller;
  839. interrupt-controller;
  840. #interrupt-cells = <0x00000002>;
  841. #size-cells = <0x00000000>;
  842. #gpio-cells = <0x00000006>;
  843. linux,phandle = <0x00000030>;
  844. phandle = <0x00000030>;
  845. uart0@1 {
  846. allwinner,pins = "PB8", "PB9";
  847. allwinner,function = "io_disabled";
  848. allwinner,muxsel = <0x00000007>;
  849. allwinner,drive = <0x00000001>;
  850. allwinner,pull = <0x00000001>;
  851. linux,phandle = <0x0000001a>;
  852. phandle = <0x0000001a>;
  853. };
  854. uart1@1 {
  855. allwinner,pins = "PG6", "PG7", "PG8", "PG9";
  856. allwinner,function = "io_disabled";
  857. allwinner,muxsel = <0x00000007>;
  858. allwinner,drive = <0x00000001>;
  859. allwinner,pull = <0x00000001>;
  860. linux,phandle = <0x0000001d>;
  861. phandle = <0x0000001d>;
  862. };
  863. uart2@1 {
  864. allwinner,pins = "PB0", "PB1", "PB2", "PB3";
  865. allwinner,function = "io_disabled";
  866. allwinner,muxsel = <0x00000007>;
  867. allwinner,drive = <0x00000001>;
  868. allwinner,pull = <0x00000001>;
  869. linux,phandle = <0x00000020>;
  870. phandle = <0x00000020>;
  871. };
  872. uart3@1 {
  873. allwinner,pins = "PH4", "PH5", "PH6", "PH7";
  874. allwinner,function = "io_disabled";
  875. allwinner,muxsel = <0x00000007>;
  876. allwinner,drive = <0x00000001>;
  877. allwinner,pull = <0x00000001>;
  878. linux,phandle = <0x00000023>;
  879. phandle = <0x00000023>;
  880. };
  881. uart4@1 {
  882. allwinner,pins = "PD2", "PD3", "PD4", "PD5";
  883. allwinner,function = "io_disabled";
  884. allwinner,muxsel = <0x00000007>;
  885. allwinner,drive = <0x00000001>;
  886. allwinner,pull = <0x00000001>;
  887. linux,phandle = <0x00000026>;
  888. phandle = <0x00000026>;
  889. };
  890. twi0@1 {
  891. allwinner,pins = "PH0", "PH1";
  892. allwinner,function = "io_disabled";
  893. allwinner,muxsel = <0x00000007>;
  894. allwinner,drive = <0x00000001>;
  895. allwinner,pull = <0x00000000>;
  896. linux,phandle = <0x00000029>;
  897. phandle = <0x00000029>;
  898. };
  899. twi1@1 {
  900. allwinner,pins = "PH2", "PH3";
  901. allwinner,function = "io_disabled";
  902. allwinner,muxsel = <0x00000007>;
  903. allwinner,drive = <0x00000001>;
  904. allwinner,pull = <0x00000000>;
  905. linux,phandle = <0x0000002c>;
  906. phandle = <0x0000002c>;
  907. };
  908. twi2@1 {
  909. allwinner,pins = "PE14", "PE15";
  910. allwinner,function = "io_disabled";
  911. allwinner,muxsel = <0x00000007>;
  912. allwinner,drive = <0x00000001>;
  913. allwinner,pull = <0x00000000>;
  914. linux,phandle = <0x0000002f>;
  915. phandle = <0x0000002f>;
  916. };
  917. spi0@2 {
  918. allwinner,pins = "PC3", "PC2", "PC0", "PC1";
  919. allwinner,function = "io_disabled";
  920. allwinner,muxsel = <0x00000007>;
  921. allwinner,drive = <0x00000001>;
  922. allwinner,pull = <0x00000000>;
  923. linux,phandle = <0x00000055>;
  924. phandle = <0x00000055>;
  925. };
  926. spi1@2 {
  927. allwinner,pins = "PD0", "PD1", "PD2", "PD3";
  928. allwinner,function = "io_disabled";
  929. allwinner,muxsel = <0x00000007>;
  930. allwinner,drive = <0x00000001>;
  931. allwinner,pull = <0x00000000>;
  932. linux,phandle = <0x00000059>;
  933. phandle = <0x00000059>;
  934. };
  935. sdc0@1 {
  936. allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
  937. allwinner,function = "io_disabled";
  938. allwinner,muxsel = <0x00000007>;
  939. allwinner,drive = <0x00000001>;
  940. allwinner,pull = <0x00000001>;
  941. linux,phandle = <0x00000064>;
  942. phandle = <0x00000064>;
  943. };
  944. sdc1@1 {
  945. allwinner,pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
  946. allwinner,function = "io_disabled";
  947. allwinner,muxsel = <0x00000007>;
  948. allwinner,drive = <0x00000001>;
  949. allwinner,pull = <0x00000001>;
  950. linux,phandle = <0x00000069>;
  951. phandle = <0x00000069>;
  952. };
  953. sdc2@1 {
  954. allwinner,pins = "PC1", "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16";
  955. allwinner,function = "io_disabled";
  956. allwinner,muxsel = <0x00000007>;
  957. allwinner,drive = <0x00000001>;
  958. allwinner,pull = <0x00000001>;
  959. linux,phandle = <0x0000005f>;
  960. phandle = <0x0000005f>;
  961. };
  962. daudio0@0 {
  963. allwinner,pins = "PB6", "PB3", "PB4", "PB5", "PB7";
  964. allwinner,function = "pcm0";
  965. allwinner,muxsel = <0x00000003>;
  966. allwinner,drive = <0x00000001>;
  967. allwinner,pull = <0x00000000>;
  968. linux,phandle = <0x00000043>;
  969. phandle = <0x00000043>;
  970. };
  971. daudio0_sleep@0 {
  972. allwinner,pins = "PB6", "PB3", "PB4", "PB5", "PB7";
  973. allwinner,function = "io_disabled";
  974. allwinner,muxsel = <0x00000007>;
  975. allwinner,drive = <0x00000001>;
  976. allwinner,pull = <0x00000000>;
  977. linux,phandle = <0x00000044>;
  978. phandle = <0x00000044>;
  979. };
  980. daudio1@0 {
  981. allwinner,pins = "PG10", "PG11", "PG12", "PG13";
  982. allwinner,function = "pcm1";
  983. allwinner,muxsel = <0x00000003>;
  984. allwinner,drive = <0x00000001>;
  985. allwinner,pull = <0x00000000>;
  986. linux,phandle = <0x00000045>;
  987. phandle = <0x00000045>;
  988. };
  989. daudio1_sleep@0 {
  990. allwinner,pins = "PG10", "PG11", "PG12", "PG13";
  991. allwinner,function = "io_disabled";
  992. allwinner,muxsel = <0x00000007>;
  993. allwinner,drive = <0x00000001>;
  994. allwinner,pull = <0x00000000>;
  995. linux,phandle = <0x00000046>;
  996. phandle = <0x00000046>;
  997. };
  998. aif3@0 {
  999. allwinner,pins = "PG10", "PG11", "PG12", "PG13";
  1000. allwinner,function = "aif3";
  1001. allwinner,muxsel = <0x00000002>;
  1002. allwinner,drive = <0x00000001>;
  1003. allwinner,pull = <0x00000000>;
  1004. linux,phandle = <0x0000003e>;
  1005. phandle = <0x0000003e>;
  1006. };
  1007. aif2_sleep@0 {
  1008. allwinner,pins = "PB6", "PB4", "PB5", "PB7";
  1009. allwinner,function = "io_disabled";
  1010. allwinner,muxsel = <0x00000007>;
  1011. allwinner,drive = <0x00000001>;
  1012. allwinner,pull = <0x00000000>;
  1013. linux,phandle = <0x0000003f>;
  1014. phandle = <0x0000003f>;
  1015. };
  1016. aif3_sleep@0 {
  1017. allwinner,pins = "PG10", "PG11", "PG12", "PG13";
  1018. allwinner,function = "io_disabled";
  1019. allwinner,muxsel = <0x00000007>;
  1020. allwinner,drive = <0x00000001>;
  1021. allwinner,pull = <0x00000000>;
  1022. linux,phandle = <0x00000040>;
  1023. phandle = <0x00000040>;
  1024. };
  1025. spdif@0 {
  1026. allwinner,pins = "PH8";
  1027. allwinner,function = "spdif0";
  1028. allwinner,muxsel = <0x00000002>;
  1029. allwinner,drive = <0x00000001>;
  1030. allwinner,pull = <0x00000000>;
  1031. linux,phandle = <0x0000004a>;
  1032. phandle = <0x0000004a>;
  1033. };
  1034. spdif_sleep@0 {
  1035. allwinner,pins = "PH8";
  1036. allwinner,function = "io_disabled";
  1037. allwinner,muxsel = <0x00000007>;
  1038. allwinner,drive = <0x00000001>;
  1039. allwinner,pull = <0x00000000>;
  1040. linux,phandle = <0x0000004b>;
  1041. phandle = <0x0000004b>;
  1042. };
  1043. csi0_sleep@0 {
  1044. allwinner,pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11", "PE12", "PE13";
  1045. allwinner,pname = "csi0_pck", "csi0_hsync", "csi0_vsync", "csi0_d0", "csi0_d1", "csi0_d2", "csi0_d3", "csi0_d4", "csi0_d5", "csi0_d6", "csi0_d7", "csi0_sck", "csi0_sda";
  1046. allwinner,function = "io_disabled";
  1047. allwinner,muxsel = <0x00000007>;
  1048. allwinner,drive = <0x00000001>;
  1049. allwinner,pull = <0x00000000>;
  1050. allwinner,data = <0x00000000>;
  1051. linux,phandle = <0x00000077>;
  1052. phandle = <0x00000077>;
  1053. };
  1054. smartcard@0 {
  1055. allwinner,pins = "PB1", "PB4", "PB5", "PB6", "PB7";
  1056. allwinner,function = "sim0";
  1057. allwinner,muxsel = <0x00000005>;
  1058. allwinner,drive = <0x00000001>;
  1059. allwinner,pull = <0x00000001>;
  1060. linux,phandle = <0x0000007f>;
  1061. phandle = <0x0000007f>;
  1062. };
  1063. nand0@2 {
  1064. allwinner,pins = "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16", "PC17", "PC18";
  1065. allwinner,function = "io_disabled";
  1066. allwinner,muxsel = <0x00000007>;
  1067. allwinner,drive = <0x00000001>;
  1068. allwinner,pull = <0x00000000>;
  1069. linux,phandle = <0x00000083>;
  1070. phandle = <0x00000083>;
  1071. };
  1072. card0_boot_para@0 {
  1073. linux,phandle = <0x00000099>;
  1074. phandle = <0x00000099>;
  1075. allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
  1076. allwinner,function = "card0_boot_para";
  1077. allwinner,pname = "sdc_d1", "sdc_d0", "sdc_clk", "sdc_cmd", "sdc_d3", "sdc_d2";
  1078. allwinner,muxsel = <0x00000002>;
  1079. allwinner,pull = <0x00000001>;
  1080. allwinner,drive = <0x00000002>;
  1081. allwinner,data = <0xffffffff>;
  1082. };
  1083. card2_boot_para@0 {
  1084. linux,phandle = <0x0000009a>;
  1085. phandle = <0x0000009a>;
  1086. allwinner,pins = "PC1", "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16";
  1087. allwinner,function = "card2_boot_para";
  1088. allwinner,pname = "sdc_ds", "sdc_clk", "sdc_cmd", "sdc_d0", "sdc_d1", "sdc_d2", "sdc_d3", "sdc_d4", "sdc_d5", "sdc_d6", "sdc_d7", "sdc_emmc_rst";
  1089. allwinner,muxsel = <0x00000003>;
  1090. allwinner,pull = <0x00000001>;
  1091. allwinner,drive = <0x00000003>;
  1092. allwinner,data = <0xffffffff>;
  1093. };
  1094. twi_para@0 {
  1095. linux,phandle = <0x0000009b>;
  1096. phandle = <0x0000009b>;
  1097. allwinner,pins = "PH0", "PH1";
  1098. allwinner,function = "twi_para";
  1099. allwinner,pname = "twi_scl", "twi_sda";
  1100. allwinner,muxsel = <0x00000002>;
  1101. allwinner,pull = <0xffffffff>;
  1102. allwinner,drive = <0xffffffff>;
  1103. allwinner,data = <0xffffffff>;
  1104. };
  1105. uart_para@0 {
  1106. linux,phandle = <0x0000009c>;
  1107. phandle = <0x0000009c>;
  1108. allwinner,pins = "PB8", "PB9";
  1109. allwinner,function = "uart_para";
  1110. allwinner,pname = "uart_debug_tx", "uart_debug_rx";
  1111. allwinner,muxsel = <0x00000004>;
  1112. allwinner,pull = <0x00000001>;
  1113. allwinner,drive = <0xffffffff>;
  1114. allwinner,data = <0xffffffff>;
  1115. };
  1116. jtag_para@0 {
  1117. linux,phandle = <0x0000009d>;
  1118. phandle = <0x0000009d>;
  1119. allwinner,pins = "PB0", "PB1", "PB2", "PB3";
  1120. allwinner,function = "jtag_para";
  1121. allwinner,pname = "jtag_ms", "jtag_ck", "jtag_do", "jtag_di";
  1122. allwinner,muxsel = <0x00000004>;
  1123. allwinner,pull = <0xffffffff>;
  1124. allwinner,drive = <0xffffffff>;
  1125. allwinner,data = <0xffffffff>;
  1126. };
  1127. gmac0@0 {
  1128. linux,phandle = <0x0000009e>;
  1129. phandle = <0x0000009e>;
  1130. allwinner,pins = "PD18", "PD17", "PD16", "PD15", "PD20", "PD19", "PD11", "PD10", "PD9", "PD8", "PD13", "PD12", "PD21", "PD22", "PD23";
  1131. allwinner,function = "gmac0";
  1132. allwinner,pname = "gmac_txd0", "gmac_txd1", "gmac_txd2", "gmac_txd3", "gmac_txen", "gmac_gtxclk", "gmac_rxd0", "gmac_rxd1", "gmac_rxd2", "gmac_rxd3", "gmac_rxdv", "gmac_rxclk", "gmac_clkin", "gmac_mdc", "gmac_mdio";
  1133. allwinner,muxsel = <0x00000004>;
  1134. allwinner,pull = <0xffffffff>;
  1135. allwinner,drive = <0xffffffff>;
  1136. allwinner,data = <0xffffffff>;
  1137. };
  1138. twi0@0 {
  1139. linux,phandle = <0x0000009f>;
  1140. phandle = <0x0000009f>;
  1141. allwinner,pins = "PH0", "PH1";
  1142. allwinner,function = "twi0";
  1143. allwinner,pname = "twi0_scl", "twi0_sda";
  1144. allwinner,muxsel = <0x00000002>;
  1145. allwinner,pull = <0xffffffff>;
  1146. allwinner,drive = <0xffffffff>;
  1147. allwinner,data = <0xffffffff>;
  1148. };
  1149. twi1@0 {
  1150. linux,phandle = <0x000000a0>;
  1151. phandle = <0x000000a0>;
  1152. allwinner,pins = "PH2", "PH3";
  1153. allwinner,function = "twi1";
  1154. allwinner,pname = "twi1_scl", "twi1_sda";
  1155. allwinner,muxsel = <0x00000002>;
  1156. allwinner,pull = <0xffffffff>;
  1157. allwinner,drive = <0xffffffff>;
  1158. allwinner,data = <0xffffffff>;
  1159. };
  1160. twi2@0 {
  1161. linux,phandle = <0x000000a1>;
  1162. phandle = <0x000000a1>;
  1163. allwinner,pins = "PE14", "PE15";
  1164. allwinner,function = "twi2";
  1165. allwinner,pname = "twi2_scl", "twi2_sda";
  1166. allwinner,muxsel = <0x00000003>;
  1167. allwinner,pull = <0xffffffff>;
  1168. allwinner,drive = <0xffffffff>;
  1169. allwinner,data = <0xffffffff>;
  1170. };
  1171. uart0@0 {
  1172. linux,phandle = <0x000000a2>;
  1173. phandle = <0x000000a2>;
  1174. allwinner,pins = "PB8", "PB9";
  1175. allwinner,function = "uart0";
  1176. allwinner,pname = "uart0_tx", "uart0_rx";
  1177. allwinner,muxsel = <0x00000004>;
  1178. allwinner,pull = <0x00000001>;
  1179. allwinner,drive = <0xffffffff>;
  1180. allwinner,data = <0xffffffff>;
  1181. };
  1182. uart1@0 {
  1183. linux,phandle = <0x000000a3>;
  1184. phandle = <0x000000a3>;
  1185. allwinner,pins = "PG6", "PG7", "PG8", "PG9";
  1186. allwinner,function = "uart1";
  1187. allwinner,pname = "uart1_tx", "uart1_rx", "uart1_rts", "uart1_cts";
  1188. allwinner,muxsel = <0x00000002>;
  1189. allwinner,pull = <0x00000001>;
  1190. allwinner,drive = <0xffffffff>;
  1191. allwinner,data = <0xffffffff>;
  1192. };
  1193. uart2@0 {
  1194. linux,phandle = <0x000000a4>;
  1195. phandle = <0x000000a4>;
  1196. allwinner,pins = "PB0", "PB1", "PB2", "PB3";
  1197. allwinner,function = "uart2";
  1198. allwinner,pname = "uart2_tx", "uart2_rx", "uart2_rts", "uart2_cts";
  1199. allwinner,muxsel = <0x00000002>;
  1200. allwinner,pull = <0x00000001>;
  1201. allwinner,drive = <0xffffffff>;
  1202. allwinner,data = <0xffffffff>;
  1203. };
  1204. uart3@0 {
  1205. linux,phandle = <0x000000a5>;
  1206. phandle = <0x000000a5>;
  1207. allwinner,pins = "PH4", "PH5", "PH6", "PH7";
  1208. allwinner,function = "uart3";
  1209. allwinner,pname = "uart3_tx", "uart3_rx", "uart3_rts", "uart3_cts";
  1210. allwinner,muxsel = <0x00000002>;
  1211. allwinner,pull = <0x00000001>;
  1212. allwinner,drive = <0xffffffff>;
  1213. allwinner,data = <0xffffffff>;
  1214. };
  1215. uart4@0 {
  1216. linux,phandle = <0x000000a6>;
  1217. phandle = <0x000000a6>;
  1218. allwinner,pins = "PD2", "PD3", "PD4", "PD5";
  1219. allwinner,function = "uart4";
  1220. allwinner,pname = "uart4_tx", "uart4_rx", "uart4_rts", "uart4_cts";
  1221. allwinner,muxsel = <0x00000003>;
  1222. allwinner,pull = <0x00000001>;
  1223. allwinner,drive = <0xffffffff>;
  1224. allwinner,data = <0xffffffff>;
  1225. };
  1226. spi0@0 {
  1227. linux,phandle = <0x000000a7>;
  1228. phandle = <0x000000a7>;
  1229. allwinner,pins = "PC3";
  1230. allwinner,function = "spi0";
  1231. allwinner,pname = "spi0_cs0";
  1232. allwinner,muxsel = <0x00000004>;
  1233. allwinner,pull = <0x00000001>;
  1234. allwinner,drive = <0xffffffff>;
  1235. allwinner,data = <0xffffffff>;
  1236. };
  1237. spi0@1 {
  1238. linux,phandle = <0x000000a8>;
  1239. phandle = <0x000000a8>;
  1240. allwinner,pins = "PC2", "PC0", "PC1";
  1241. allwinner,function = "spi0";
  1242. allwinner,pname = "spi0_sclk", "spi0_mosi", "spi0_miso";
  1243. allwinner,muxsel = <0x00000004>;
  1244. allwinner,pull = <0xffffffff>;
  1245. allwinner,drive = <0xffffffff>;
  1246. allwinner,data = <0xffffffff>;
  1247. };
  1248. spi1@0 {
  1249. linux,phandle = <0x000000a9>;
  1250. phandle = <0x000000a9>;
  1251. allwinner,pins = "PD0";
  1252. allwinner,function = "spi1";
  1253. allwinner,pname = "spi1_cs0";
  1254. allwinner,muxsel = <0x00000004>;
  1255. allwinner,pull = <0x00000001>;
  1256. allwinner,drive = <0xffffffff>;
  1257. allwinner,data = <0xffffffff>;
  1258. };
  1259. spi1@1 {
  1260. linux,phandle = <0x000000aa>;
  1261. phandle = <0x000000aa>;
  1262. allwinner,pins = "PD1", "PD2", "PD3";
  1263. allwinner,function = "spi1";
  1264. allwinner,pname = "spi1_sclk", "spi1_mosi", "spi1_miso";
  1265. allwinner,muxsel = <0x00000004>;
  1266. allwinner,pull = <0xffffffff>;
  1267. allwinner,drive = <0xffffffff>;
  1268. allwinner,data = <0xffffffff>;
  1269. };
  1270. nand0@0 {
  1271. linux,phandle = <0x000000ab>;
  1272. phandle = <0x000000ab>;
  1273. allwinner,pins = "PC0", "PC1", "PC2", "PC5", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16";
  1274. allwinner,function = "nand0";
  1275. allwinner,pname = "nand0_we", "nand0_ale", "nand0_cle", "nand0_nre", "nand0_d0", "nand0_d1", "nand0_d2", "nand0_d3", "nand0_d4", "nand0_d5", "nand0_d6", "nand0_d7", "nand0_ndqs";
  1276. allwinner,muxsel = <0x00000002>;
  1277. allwinner,pull = <0x00000000>;
  1278. allwinner,drive = <0x00000001>;
  1279. allwinner,data = <0xffffffff>;
  1280. };
  1281. nand0@1 {
  1282. linux,phandle = <0x000000ac>;
  1283. phandle = <0x000000ac>;
  1284. allwinner,pins = "PC3", "PC4", "PC6", "PC7", "PC17", "PC18";
  1285. allwinner,function = "nand0";
  1286. allwinner,pname = "nand0_ce1", "nand0_ce0", "nand0_rb0", "nand0_rb1", "nand0_ce2", "nand0_ce3";
  1287. allwinner,muxsel = <0x00000002>;
  1288. allwinner,pull = <0x00000001>;
  1289. allwinner,drive = <0x00000001>;
  1290. allwinner,data = <0xffffffff>;
  1291. };
  1292. pwm0@0 {
  1293. linux,phandle = <0x000000ad>;
  1294. phandle = <0x000000ad>;
  1295. allwinner,pins = "PD22";
  1296. allwinner,function = "pwm0";
  1297. allwinner,pname = "pwm_positive";
  1298. allwinner,muxsel = <0x00000002>;
  1299. allwinner,pull = <0x00000000>;
  1300. allwinner,drive = <0xffffffff>;
  1301. allwinner,data = <0xffffffff>;
  1302. };
  1303. pwm0@1 {
  1304. linux,phandle = <0x000000ae>;
  1305. phandle = <0x000000ae>;
  1306. allwinner,pins = "PD22";
  1307. allwinner,function = "pwm0";
  1308. allwinner,pname = "pwm_positive";
  1309. allwinner,muxsel = <0x00000007>;
  1310. allwinner,pull = <0x00000000>;
  1311. allwinner,drive = <0xffffffff>;
  1312. allwinner,data = <0xffffffff>;
  1313. };
  1314. csi0@0 {
  1315. linux,phandle = <0x000000b1>;
  1316. phandle = <0x000000b1>;
  1317. allwinner,pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11", "PE12", "PE13";
  1318. allwinner,function = "csi0";
  1319. allwinner,pname = "csi0_pck", "csi0_hsync", "csi0_vsync", "csi0_d0", "csi0_d1", "csi0_d2", "csi0_d3", "csi0_d4", "csi0_d5", "csi0_d6", "csi0_d7", "csi0_sck", "csi0_sda";
  1320. allwinner,muxsel = <0x00000002>;
  1321. allwinner,pull = <0xffffffff>;
  1322. allwinner,drive = <0xffffffff>;
  1323. allwinner,data = <0xffffffff>;
  1324. };
  1325. sdc0@0 {
  1326. linux,phandle = <0x000000b2>;
  1327. phandle = <0x000000b2>;
  1328. allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
  1329. allwinner,function = "sdc0";
  1330. allwinner,pname = "sdc0_d1", "sdc0_d0", "sdc0_clk", "sdc0_cmd", "sdc0_d3", "sdc0_d2";
  1331. allwinner,muxsel = <0x00000002>;
  1332. allwinner,pull = <0x00000001>;
  1333. allwinner,drive = <0x00000002>;
  1334. allwinner,data = <0xffffffff>;
  1335. };
  1336. sdc1@0 {
  1337. linux,phandle = <0x000000b3>;
  1338. phandle = <0x000000b3>;
  1339. allwinner,pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
  1340. allwinner,function = "sdc1";
  1341. allwinner,pname = "sdc1_clk", "sdc1_cmd", "sdc1_d0", "sdc1_d1", "sdc1_d2", "sdc1_d3";
  1342. allwinner,muxsel = <0x00000002>;
  1343. allwinner,pull = <0x00000001>;
  1344. allwinner,drive = <0x00000003>;
  1345. allwinner,data = <0xffffffff>;
  1346. };
  1347. sdc2@0 {
  1348. linux,phandle = <0x000000b4>;
  1349. phandle = <0x000000b4>;
  1350. allwinner,pins = "PC1", "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16";
  1351. allwinner,function = "sdc2";
  1352. allwinner,pname = "sdc2_ds", "sdc2_clk", "sdc2_cmd", "sdc2_d0", "sdc2_d1", "sdc2_d2", "sdc2_d3", "sdc2_d4", "sdc2_d5", "sdc2_d6", "sdc2_d7", "sdc2_emmc_rst";
  1353. allwinner,muxsel = <0x00000003>;
  1354. allwinner,pull = <0x00000001>;
  1355. allwinner,drive = <0x00000003>;
  1356. allwinner,data = <0xffffffff>;
  1357. };
  1358. codec@0 {
  1359. linux,phandle = <0x000000b5>;
  1360. phandle = <0x000000b5>;
  1361. allwinner,pins = "PH7";
  1362. allwinner,function = "codec";
  1363. allwinner,pname = "gpio-spk";
  1364. allwinner,muxsel = <0x00000002>;
  1365. allwinner,pull = <0x00000001>;
  1366. allwinner,drive = <0xffffffff>;
  1367. allwinner,data = <0xffffffff>;
  1368. };
  1369. Vdevice@0 {
  1370. linux,phandle = <0x000000b9>;
  1371. phandle = <0x000000b9>;
  1372. allwinner,pins = "PB1", "PB2";
  1373. allwinner,function = "Vdevice";
  1374. allwinner,pname = "Vdevice_0", "Vdevice_1";
  1375. allwinner,muxsel = <0x00000004>;
  1376. allwinner,pull = <0x00000001>;
  1377. allwinner,drive = <0x00000002>;
  1378. allwinner,data = <0xffffffff>;
  1379. };
  1380. };
  1381. pinctrl@0 {
  1382. compatible = "allwinner,axp-pinctrl";
  1383. gpio-controller;
  1384. #size-cells = <0x00000000>;
  1385. #gpio-cells = <0x00000006>;
  1386. device_type = "axp_pio";
  1387. linux,phandle = <0x00000031>;
  1388. phandle = <0x00000031>;
  1389. };
  1390. dma-controller@01c02000 {
  1391. compatible = "allwinner,sun50i-dma";
  1392. reg = <0x00000000 0x01c02000 0x00000000 0x00001000>;
  1393. interrupts = <0x00000000 0x00000032 0x00000004>;
  1394. clocks = <0x0000000b>;
  1395. #dma-cells = <0x00000001>;
  1396. };
  1397. mbus-controller@01c62000 {
  1398. compatible = "allwinner,sun50i-mbus";
  1399. reg = <0x00000000 0x01c62000 0x00000000 0x00000110>;
  1400. #mbus-cells = <0x00000001>;
  1401. };
  1402. arisc {
  1403. compatible = "allwinner,sunxi-arisc";
  1404. #address-cells = <0x00000002>;
  1405. #size-cells = <0x00000002>;
  1406. clocks = <0x0000000c 0x0000000d 0x00000006 0x00000004>;
  1407. clock-names = "losc", "iosc", "hosc", "pll_periph0";
  1408. powchk_used = <0x00000000>;
  1409. power_reg = <0x02309621>;
  1410. system_power = <0x00000032>;
  1411. };
  1412. arisc_space {
  1413. compatible = "allwinner,arisc_space";
  1414. space1 = <0x00040000 0x00000000 0x00014000>;
  1415. space2 = <0x40100000 0x00018000 0x00004000>;
  1416. space3 = <0x40104000 0x00000000 0x00001000>;
  1417. space4 = <0x40105000 0x00000000 0x00001000>;
  1418. };
  1419. standby_space {
  1420. compatible = "allwinner,standby_space";
  1421. space1 = <0x41020000 0x00000000 0x00000800>;
  1422. };
  1423. msgbox@1c17000 {
  1424. compatible = "allwinner,msgbox";
  1425. clocks = <0x0000000e>;
  1426. clock-names = "clk_msgbox";
  1427. reg = <0x00000000 0x01c17000 0x00000000 0x00001000>;
  1428. interrupts = <0x00000000 0x00000031 0x00000001>;
  1429. status = "okay";
  1430. };
  1431. hwspinlock@1c18000 {
  1432. compatible = "allwinner,sunxi-hwspinlock";
  1433. clocks = <0x0000000f 0x00000010>;
  1434. clock-names = "clk_hwspinlock_rst", "clk_hwspinlock_bus";
  1435. reg = <0x00000000 0x01c18000 0x00000000 0x00001000>;
  1436. status = "okay";
  1437. num-locks = <0x00000008>;
  1438. };
  1439. s_cir@1f02000 {
  1440. compatible = "allwinner,s_cir";
  1441. reg = <0x00000000 0x01f02000 0x00000000 0x00000400>;
  1442. interrupts = <0x00000000 0x00000025 0x00000004>;
  1443. pinctrl-names = "default";
  1444. pinctrl-0 = <0x00000011>;
  1445. clocks = <0x00000006 0x00000012>;
  1446. supply = "vcc-pl";
  1447. ir_power_key_code = <0x0000004d>;
  1448. ir_addr_code = <0x00004040>;
  1449. status = "okay";
  1450. device_type = "s_cir0";
  1451. };
  1452. s_uart@1f02800 {
  1453. compatible = "allwinner,s_uart";
  1454. reg = <0x00000000 0x01f02800 0x00000000 0x00000400>;
  1455. interrupts = <0x00000000 0x00000026 0x00000004>;
  1456. pinctrl-names = "default";
  1457. status = "okay";
  1458. device_type = "s_uart0";
  1459. pinctrl-0 = <0x000000b6>;
  1460. };
  1461. s_rsb@1f03400 {
  1462. compatible = "allwinner,s_rsb";
  1463. reg = <0x00000000 0x01f03400 0x00000000 0x00000400>;
  1464. interrupts = <0x00000000 0x00000027 0x00000004>;
  1465. pinctrl-names = "default";
  1466. status = "okay";
  1467. device_type = "s_rsb0";
  1468. pinctrl-0 = <0x000000b7>;
  1469. };
  1470. s_jtag0 {
  1471. compatible = "allwinner,s_jtag";
  1472. pinctrl-names = "default";
  1473. status = "disabled";
  1474. device_type = "s_jtag0";
  1475. pinctrl-0 = <0x000000b8>;
  1476. };
  1477. timer@1c20c00 {
  1478. compatible = "allwinner,sunxi-timer";
  1479. device_type = "timer";
  1480. reg = <0x00000000 0x01c20c00 0x00000000 0x00000090>;
  1481. interrupts = <0x00000000 0x00000012 0x00000001>;
  1482. clock-frequency = <0x016e3600>;
  1483. timer-prescale = <0x00000010>;
  1484. };
  1485. rtc@01f00000 {
  1486. compatible = "allwinner,sun50i-rtc";
  1487. device_type = "rtc";
  1488. reg = <0x00000000 0x01f00000 0x00000000 0x00000218>;
  1489. interrupts = <0x00000000 0x00000028 0x00000004>;
  1490. gpr_offset = <0x00000100>;
  1491. gpr_len = <0x00000004>;
  1492. };
  1493. ve@01c0e000 {
  1494. compatible = "allwinner,sunxi-cedar-ve";
  1495. reg = <0x00000000 0x01c0e000 0x00000000 0x00001000 0x00000000 0x01c00000 0x00000000 0x00000010 0x00000000 0x01c20000 0x00000000 0x00000800>;
  1496. interrupts = <0x00000000 0x0000003a 0x00000004>;
  1497. clocks = <0x00000016 0x00000017>;
  1498. };
  1499. uart@01c28000 {
  1500. compatible = "allwinner,sun50i-uart";
  1501. device_type = "uart0";
  1502. reg = <0x00000000 0x01c28000 0x00000000 0x00000400>;
  1503. interrupts = <0x00000000 0x00000000 0x00000004>;
  1504. clocks = <0x00000018>;
  1505. pinctrl-names = "default", "sleep";
  1506. pinctrl-1 = <0x0000001a>;
  1507. uart0_port = <0x00000000>;
  1508. uart0_type = <0x00000002>;
  1509. status = "okay";
  1510. pinctrl-0 = <0x000000a2>;
  1511. };
  1512. uart@01c28400 {
  1513. compatible = "allwinner,sun50i-uart";
  1514. device_type = "uart1";
  1515. reg = <0x00000000 0x01c28400 0x00000000 0x00000400>;
  1516. interrupts = <0x00000000 0x00000001 0x00000004>;
  1517. clocks = <0x0000001b>;
  1518. pinctrl-names = "default", "sleep";
  1519. pinctrl-1 = <0x0000001d>;
  1520. uart1_port = <0x00000001>;
  1521. uart1_type = <0x00000004>;
  1522. status = "okay";
  1523. pinctrl-0 = <0x000000a3>;
  1524. };
  1525. uart@01c28800 {
  1526. compatible = "allwinner,sun50i-uart";
  1527. device_type = "uart2";
  1528. reg = <0x00000000 0x01c28800 0x00000000 0x00000400>;
  1529. interrupts = <0x00000000 0x00000002 0x00000004>;
  1530. clocks = <0x0000001e>;
  1531. pinctrl-names = "default", "sleep";
  1532. pinctrl-1 = <0x00000020>;
  1533. uart2_port = <0x00000002>;
  1534. uart2_type = <0x00000004>;
  1535. status = "disabled";
  1536. pinctrl-0 = <0x000000a4>;
  1537. };
  1538. uart@01c28c00 {
  1539. compatible = "allwinner,sun50i-uart";
  1540. device_type = "uart3";
  1541. reg = <0x00000000 0x01c28c00 0x00000000 0x00000400>;
  1542. interrupts = <0x00000000 0x00000003 0x00000004>;
  1543. clocks = <0x00000021>;
  1544. pinctrl-names = "default", "sleep";
  1545. pinctrl-1 = <0x00000023>;
  1546. uart3_port = <0x00000003>;
  1547. uart3_type = <0x00000004>;
  1548. status = "disabled";
  1549. pinctrl-0 = <0x000000a5>;
  1550. };
  1551. uart@01c29000 {
  1552. compatible = "allwinner,sun50i-uart";
  1553. device_type = "uart4";
  1554. reg = <0x00000000 0x01c29000 0x00000000 0x00000400>;
  1555. interrupts = <0x00000000 0x00000004 0x00000004>;
  1556. clocks = <0x00000024>;
  1557. pinctrl-names = "default", "sleep";
  1558. pinctrl-1 = <0x00000026>;
  1559. uart4_port = <0x00000004>;
  1560. uart4_type = <0x00000004>;
  1561. status = "disabled";
  1562. pinctrl-0 = <0x000000a6>;
  1563. };
  1564. twi@0x01c2ac00 {
  1565. #address-cells = <0x00000001>;
  1566. #size-cells = <0x00000000>;
  1567. compatible = "allwinner,sun50i-twi";
  1568. device_type = "twi0";
  1569. reg = <0x00000000 0x01c2ac00 0x00000000 0x00000400>;
  1570. interrupts = <0x00000000 0x00000006 0x00000004>;
  1571. clocks = <0x00000027>;
  1572. clock-frequency = <0x00061a80>;
  1573. pinctrl-names = "default", "sleep";
  1574. pinctrl-1 = <0x00000029>;
  1575. status = "okay";
  1576. pinctrl-0 = <0x0000009f>;
  1577. };
  1578. twi@0x01c2b000 {
  1579. #address-cells = <0x00000001>;
  1580. #size-cells = <0x00000000>;
  1581. compatible = "allwinner,sun50i-twi";
  1582. device_type = "twi1";
  1583. reg = <0x00000000 0x01c2b000 0x00000000 0x00000400>;
  1584. interrupts = <0x00000000 0x00000007 0x00000004>;
  1585. clocks = <0x0000002a>;
  1586. clock-frequency = <0x00030d40>;
  1587. pinctrl-names = "default", "sleep";
  1588. pinctrl-1 = <0x0000002c>;
  1589. status = "okay";
  1590. pinctrl-0 = <0x000000a0>;
  1591. };
  1592. twi@0x01c2b400 {
  1593. #address-cells = <0x00000001>;
  1594. #size-cells = <0x00000000>;
  1595. compatible = "allwinner,sun50i-twi";
  1596. device_type = "twi2";
  1597. reg = <0x00000000 0x01c2b400 0x00000000 0x00000400>;
  1598. interrupts = <0x00000000 0x00000008 0x00000004>;
  1599. clocks = <0x0000002d>;
  1600. clock-frequency = <0x00030d40>;
  1601. pinctrl-names = "default", "sleep";
  1602. pinctrl-1 = <0x0000002f>;
  1603. status = "disabled";
  1604. pinctrl-0 = <0x000000a1>;
  1605. };
  1606. usbc0@0 {
  1607. device_type = "usbc0";
  1608. compatible = "allwinner,sunxi-otg-manager";
  1609. usb_port_type = <0x00000001>;
  1610. usb_detect_type = <0x00000000>;
  1611. usb_host_init_state = <0x00000001>;
  1612. usb_regulator_io = "nocare";
  1613. usb_wakeup_suspend = <0x00000001>;
  1614. usb_luns = <0x00000003>;
  1615. usb_serial_unique = <0x00000001>;
  1616. usb_serial_number = "20080411";
  1617. rndis_wceis = <0x00000001>;
  1618. status = "okay";
  1619. usb_id_gpio;
  1620. usb_det_vbus_gpio;
  1621. usb_drv_vbus_gpio;
  1622. };
  1623. udc-controller@0x01c19000 {
  1624. compatible = "allwinner,sunxi-udc";
  1625. reg = <0x00000000 0x01c19000 0x00000000 0x00001000 0x00000000 0x01c00000 0x00000000 0x00000100>;
  1626. interrupts = <0x00000000 0x00000047 0x00000004>;
  1627. clocks = <0x00000032 0x00000033>;
  1628. status = "okay";
  1629. };
  1630. ehci0-controller@0x01c1a000 {
  1631. compatible = "allwinner,sunxi-ehci0";
  1632. reg = <0x00000000 0x01c1a000 0x00000000 0x00000fff 0x00000000 0x01c00000 0x00000000 0x00000100 0x00000000 0x01c19000 0x00000000 0x00001000>;
  1633. interrupts = <0x00000000 0x00000048 0x00000004>;
  1634. clocks = <0x00000032 0x00000034>;
  1635. hci_ctrl_no = <0x00000000>;
  1636. status = "okay";
  1637. };
  1638. ohci0-controller@0x01c1a400 {
  1639. compatible = "allwinner,sunxi-ohci0";
  1640. reg = <0x00000000 0x01c1a000 0x00000000 0x00000fff 0x00000000 0x01c00000 0x00000000 0x00000100 0x00000000 0x01c19000 0x00000000 0x00001000>;
  1641. interrupts = <0x00000000 0x00000049 0x00000004>;
  1642. clocks = <0x00000032 0x00000035>;
  1643. hci_ctrl_no = <0x00000000>;
  1644. status = "okay";
  1645. };
  1646. usbc1@0 {
  1647. device_type = "usbc1";
  1648. usb_host_init_state = <0x00000001>;
  1649. usb_regulator_io = "nocare";
  1650. usb_wakeup_suspend = <0x00000001>;
  1651. usb_hsic_used = <0x00000000>;
  1652. usb_hsic_regulator_io = "vcc-hsic-12";
  1653. usb_hsic_ctrl = <0x00000000>;
  1654. usb_hsic_usb3503_flag = <0x00000000>;
  1655. status = "okay";
  1656. usb_port_type = <0x00000001>;
  1657. usb_detect_type = <0x00000000>;
  1658. usb_drv_vbus_gpio;
  1659. usb_hsic_rdy_gpio;
  1660. usb_hsic_hub_connect_gpio;
  1661. usb_hsic_int_n_gpio;
  1662. usb_hsic_reset_n_gpio;
  1663. };
  1664. ehci1-controller@0x01c1b000 {
  1665. compatible = "allwinner,sunxi-ehci1";
  1666. reg = <0x00000000 0x01c1b000 0x00000000 0x00000fff 0x00000000 0x01c00000 0x00000000 0x00000100 0x00000000 0x01c19000 0x00000000 0x00001000>;
  1667. interrupts = <0x00000000 0x0000004a 0x00000004>;
  1668. clocks = <0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a>;
  1669. hci_ctrl_no = <0x00000001>;
  1670. status = "okay";
  1671. };
  1672. ohci1-controller@0x01c1b400 {
  1673. compatible = "allwinner,sunxi-ohci1";
  1674. reg = <0x00000000 0x01c1b000 0x00000000 0x00000fff 0x00000000 0x01c00000 0x00000000 0x00000100 0x00000000 0x01c19000 0x00000000 0x00001000>;
  1675. interrupts = <0x00000000 0x0000004b 0x00000004>;
  1676. clocks = <0x00000036 0x0000003b>;
  1677. hci_ctrl_no = <0x00000001>;
  1678. status = "okay";
  1679. };
  1680. codec@0x01c22c00 {
  1681. compatible = "allwinner,sunxi-internal-codec";
  1682. reg = <0x00000000 0x01c22c00 0x00000000 0x00000478 0x00000000 0x01f015c0 0x00000000 0x00000000>;
  1683. clocks = <0x0000003c>;
  1684. pinctrl-names = "aif2-default", "aif3-default", "aif2-sleep", "aif3-sleep";
  1685. pinctrl-1 = <0x0000003e>;
  1686. pinctrl-2 = <0x0000003f>;
  1687. pinctrl-3 = <0x00000040>;
  1688. gpio-spk = <0x00000030 0x00000007 0x00000007 0x00000001 0x00000001 0x00000001 0x00000001>;
  1689. headphonevol = <0x0000003b>;
  1690. spkervol = <0x0000001a>;
  1691. earpiecevol = <0x0000001e>;
  1692. maingain = <0x00000004>;
  1693. headsetmicgain = <0x00000004>;
  1694. adcagc_cfg = <0x00000000>;
  1695. adcdrc_cfg = <0x00000000>;
  1696. adchpf_cfg = <0x00000000>;
  1697. dacdrc_cfg = <0x00000000>;
  1698. dachpf_cfg = <0x00000000>;
  1699. aif1_lrlk_div = <0x00000040>;
  1700. aif2_lrlk_div = <0x00000040>;
  1701. aif2config = <0x00000000>;
  1702. aif3config = <0x00000000>;
  1703. pa_sleep_time = <0x0000015e>;
  1704. dac_digital_vol = <0x0000a0a0>;
  1705. status = "okay";
  1706. linux,phandle = <0x0000004d>;
  1707. phandle = <0x0000004d>;
  1708. device_type = "codec";
  1709. pinctrl-0 = <0x000000b5>;
  1710. };
  1711. i2s0-controller@0x01c22c00 {
  1712. compatible = "allwinner,sunxi-internal-i2s";
  1713. reg = <0x00000000 0x01c22c00 0x00000000 0x00000478>;
  1714. clocks = <0x00000002 0x00000041>;
  1715. status = "okay";
  1716. linux,phandle = <0x0000004c>;
  1717. phandle = <0x0000004c>;
  1718. device_type = "i2s";
  1719. };
  1720. daudio@0x01c22000 {
  1721. compatible = "allwinner,sunxi-daudio";
  1722. reg = <0x00000000 0x01c22000 0x00000000 0x00000058>;
  1723. clocks = <0x00000002 0x00000042>;
  1724. pinctrl-names = "default", "sleep";
  1725. pinctrl-0 = <0x00000043>;
  1726. pinctrl-1 = <0x00000044>;
  1727. pcm_lrck_period = <0x00000020>;
  1728. pcm_lrckr_period = <0x00000001>;
  1729. slot_width_select = <0x00000020>;
  1730. pcm_lsb_first = <0x00000000>;
  1731. tx_data_mode = <0x00000000>;
  1732. rx_data_mode = <0x00000000>;
  1733. daudio_master = <0x00000004>;
  1734. audio_format = <0x00000001>;
  1735. signal_inversion = <0x00000001>;
  1736. frametype = <0x00000000>;
  1737. tdm_config = <0x00000001>;
  1738. tdm_num = <0x00000000>;
  1739. status = "disabled";
  1740. linux,phandle = <0x0000004e>;
  1741. phandle = <0x0000004e>;
  1742. device_type = "daudio0";
  1743. };
  1744. daudio@0x01c22400 {
  1745. compatible = "allwinner,sunxi-daudio";
  1746. reg = <0x00000000 0x01c22400 0x00000000 0x00000058>;
  1747. pinctrl-names = "default", "sleep";
  1748. pinctrl-0 = <0x00000045>;
  1749. pinctrl-1 = <0x00000046>;
  1750. clocks = <0x00000002 0x00000047>;
  1751. pcm_lrck_period = <0x00000020>;
  1752. pcm_lrckr_period = <0x00000001>;
  1753. slot_width_select = <0x00000020>;
  1754. pcm_lsb_first = <0x00000000>;
  1755. tx_data_mode = <0x00000000>;
  1756. rx_data_mode = <0x00000000>;
  1757. daudio_master = <0x00000004>;
  1758. audio_format = <0x00000001>;
  1759. signal_inversion = <0x00000001>;
  1760. frametype = <0x00000000>;
  1761. tdm_config = <0x00000001>;
  1762. tdm_num = <0x00000001>;
  1763. status = "disabled";
  1764. linux,phandle = <0x0000004f>;
  1765. phandle = <0x0000004f>;
  1766. device_type = "daudio1";
  1767. };
  1768. daudio@0x01c22800 {
  1769. compatible = "allwinner,sunxi-tdmhdmi";
  1770. reg = <0x00000000 0x01c22800 0x00000000 0x00000058>;
  1771. clocks = <0x00000002 0x00000048>;
  1772. status = "okay";
  1773. linux,phandle = <0x00000050>;
  1774. phandle = <0x00000050>;
  1775. device_type = "daudio2";
  1776. };
  1777. spdif-controller@0x01c21000 {
  1778. compatible = "allwinner,sunxi-spdif";
  1779. reg = <0x00000000 0x01c21000 0x00000000 0x00000038>;
  1780. clocks = <0x00000002 0x00000049>;
  1781. pinctrl-names = "default", "sleep";
  1782. pinctrl-0 = <0x0000004a>;
  1783. pinctrl-1 = <0x0000004b>;
  1784. status = "disabled";
  1785. linux,phandle = <0x00000051>;
  1786. phandle = <0x00000051>;
  1787. device_type = "spdif";
  1788. };
  1789. sound@0 {
  1790. compatible = "allwinner,sunxi-codec-machine";
  1791. interrupts = <0x00000000 0x0000001c 0x00000004>;
  1792. sunxi,i2s-controller = <0x0000004c>;
  1793. sunxi,audio-codec = <0x0000004d>;
  1794. aif2fmt = <0x00000003>;
  1795. aif3fmt = <0x00000003>;
  1796. aif2master = <0x00000001>;
  1797. hp_detect_case = <0x00000001>;
  1798. status = "okay";
  1799. device_type = "sndcodec";
  1800. };
  1801. sound@1 {
  1802. compatible = "allwinner,sunxi-daudio0-machine";
  1803. sunxi,daudio0-controller = <0x0000004e>;
  1804. status = "disabled";
  1805. device_type = "snddaudio0";
  1806. };
  1807. sound@2 {
  1808. compatible = "allwinner,sunxi-daudio1-machine";
  1809. sunxi,daudio1-controller = <0x0000004f>;
  1810. status = "disabled";
  1811. device_type = "snddaudio1";
  1812. };
  1813. sound@3 {
  1814. compatible = "allwinner,sunxi-hdmi-machine";
  1815. sunxi,hdmi-controller = <0x00000050>;
  1816. status = "okay";
  1817. device_type = "sndhdmi";
  1818. };
  1819. sound@4 {
  1820. compatible = "allwinner,sunxi-spdif-machine";
  1821. sunxi,spdif-controller = <0x00000051>;
  1822. status = "disabled";
  1823. device_type = "sndspdif";
  1824. };
  1825. spi@01c68000 {
  1826. #address-cells = <0x00000001>;
  1827. #size-cells = <0x00000000>;
  1828. compatible = "allwinner,sun50i-spi";
  1829. device_type = "spi0";
  1830. reg = <0x00000000 0x01c68000 0x00000000 0x00001000>;
  1831. interrupts = <0x00000000 0x00000041 0x00000004>;
  1832. clocks = <0x00000004 0x00000052>;
  1833. clock-frequency = <0x05f5e100>;
  1834. pinctrl-names = "default", "sleep";
  1835. pinctrl-1 = <0x00000055>;
  1836. spi0_cs_number = <0x00000001>;
  1837. spi0_cs_bitmap = <0x00000001>;
  1838. status = "disabled";
  1839. pinctrl-0 = <0x000000a7 0x000000a8>;
  1840. };
  1841. spi@01c69000 {
  1842. #address-cells = <0x00000001>;
  1843. #size-cells = <0x00000000>;
  1844. compatible = "allwinner,sun50i-spi";
  1845. device_type = "spi1";
  1846. reg = <0x00000000 0x01c69000 0x00000000 0x00001000>;
  1847. interrupts = <0x00000000 0x00000042 0x00000004>;
  1848. clocks = <0x00000004 0x00000056>;
  1849. clock-frequency = <0x05f5e100>;
  1850. pinctrl-names = "default", "sleep";
  1851. pinctrl-1 = <0x00000059>;
  1852. spi1_cs_number = <0x00000001>;
  1853. spi1_cs_bitmap = <0x00000001>;
  1854. status = "disabled";
  1855. pinctrl-0 = <0x000000a9 0x000000aa>;
  1856. };
  1857. sdmmc@01C11000 {
  1858. compatible = "allwinner,sun50i-sdmmc2";
  1859. device_type = "sdc2";
  1860. reg = <0x00000000 0x01c11000 0x00000000 0x00001000>;
  1861. interrupts = <0x00000000 0x0000003e 0x00000104>;
  1862. clocks = <0x00000006 0x0000005a 0x0000005b 0x0000005c 0x0000005d>;
  1863. clock-names = "osc24m", "pll_periph", "mmc", "ahb", "rst";
  1864. pinctrl-names = "default", "sleep";
  1865. pinctrl-1 = <0x0000005f>;
  1866. bus-width = <0x00000008>;
  1867. max-frequency = <0x05f5e100>;
  1868. sdc_tm4_sm0_freq0 = <0x00000000>;
  1869. sdc_tm4_sm0_freq1 = <0x00000000>;
  1870. sdc_tm4_sm1_freq0 = <0x00000000>;
  1871. sdc_tm4_sm1_freq1 = <0x00000000>;
  1872. sdc_tm4_sm2_freq0 = <0x00000000>;
  1873. sdc_tm4_sm2_freq1 = <0x00000000>;
  1874. sdc_tm4_sm3_freq0 = <0x05000000>;
  1875. sdc_tm4_sm3_freq1 = <0x00000405>;
  1876. sdc_tm4_sm4_freq0 = <0x00050000>;
  1877. sdc_tm4_sm4_freq1 = <0x00000408>;
  1878. status = "disabled";
  1879. non-removable;
  1880. pinctrl-0 = <0x000000b4>;
  1881. cd-gpios;
  1882. sunxi-power-save-mode;
  1883. sunxi-dis-signal-vol-sw;
  1884. mmc-ddr-1_8v;
  1885. mmc-hs200-1_8v;
  1886. mmc-hs400-1_8v;
  1887. vmmc = "vcc-emmc";
  1888. vqmmc = "vcc-lpddr";
  1889. vdmmc = "none";
  1890. };
  1891. sdmmc@01c0f000 {
  1892. compatible = "allwinner,sun50i-sdmmc0";
  1893. device_type = "sdc0";
  1894. reg = <0x00000000 0x01c0f000 0x00000000 0x00001000>;
  1895. interrupts = <0x00000000 0x0000003c 0x00000104>;
  1896. clocks = <0x00000006 0x0000005a 0x00000060 0x00000061 0x00000062>;
  1897. clock-names = "osc24m", "pll_periph", "mmc", "ahb", "rst";
  1898. pinctrl-names = "default", "sleep";
  1899. pinctrl-1 = <0x00000064>;
  1900. max-frequency = <0x02faf080>;
  1901. bus-width = <0x00000004>;
  1902. broken-cd;
  1903. status = "okay";
  1904. pinctrl-0 = <0x000000b2>;
  1905. cd-gpios = <0x00000030 0x00000005 0x00000006 0x00000000 0x00000001 0x00000002 0xffffffff>;
  1906. sunxi-power-save-mode;
  1907. vmmc = "none";
  1908. vqmmc = "none";
  1909. vdmmc = "vcc-sdc";
  1910. };
  1911. sdmmc@1C10000 {
  1912. compatible = "allwinner,sun50i-sdmmc1";
  1913. device_type = "sdc1";
  1914. reg = <0x00000000 0x01c10000 0x00000000 0x00001000>;
  1915. interrupts = <0x00000000 0x0000003d 0x00000104>;
  1916. clocks = <0x00000006 0x0000005a 0x00000065 0x00000066 0x00000067>;
  1917. clock-names = "osc24m", "pll_periph", "mmc", "ahb", "rst";
  1918. pinctrl-names = "default", "sleep";
  1919. pinctrl-1 = <0x00000069>;
  1920. max-frequency = <0x08f0d180>;
  1921. bus-width = <0x00000004>;
  1922. sunxi-dly-52M-ddr4 = <0x00000001 0x00000000 0x00000000 0x00000000 0x00000002>;
  1923. sunxi-dly-104M = <0x00000001 0x00000000 0x00000000 0x00000000 0x00000001>;
  1924. sunxi-dly-208M = <0x00000001 0x00000000 0x00000000 0x00000000 0x00000001>;
  1925. status = "okay";
  1926. pinctrl-0 = <0x000000b3>;
  1927. sd-uhs-sdr50;
  1928. sd-uhs-ddr50;
  1929. sd-uhs-sdr104;
  1930. cap-sdio-irq;
  1931. keep-power-in-suspend;
  1932. ignore-pm-notify;
  1933. };
  1934. disp@01000000 {
  1935. fb_base = <0x47400000>;
  1936. boot_disp = <0x0000040a>;
  1937. compatible = "allwinner,sun50i-disp";
  1938. reg = <0x00000000 0x01000000 0x00000000 0x00300000 0x00000000 0x01c0c000 0x00000000 0x000017fc 0x00000000 0x01ca0000 0x00000000 0x000010fc>;
  1939. interrupts = <0x00000000 0x00000056 0x00000104 0x00000000 0x00000057 0x00000104 0x00000000 0x00000059 0x00000104>;
  1940. clocks = <0x0000006a 0x0000006b 0x0000006c 0x0000006d 0x0000006e>;
  1941. status = "okay";
  1942. device_type = "disp";
  1943. disp_init_enable = <0x00000001>;
  1944. disp_mode = <0x00000000>;
  1945. screen0_output_type = <0x00000003>;
  1946. screen0_output_mode = <0x0000000a>;
  1947. screen1_output_type = <0x00000003>;
  1948. screen1_output_mode = <0x0000000a>;
  1949. fb0_format = <0x00000000>;
  1950. fb0_width = <0x00000000>;
  1951. fb0_height = <0x00000000>;
  1952. fb1_format = <0x00000000>;
  1953. fb1_width = <0x00000000>;
  1954. fb1_height = <0x00000000>;
  1955. };
  1956. lcd0@01c0c000 {
  1957. compatible = "allwinner,sunxi-lcd0";
  1958. pinctrl-names = "active", "sleep";
  1959. status = "okay";
  1960. device_type = "lcd0";
  1961. lcd_used = <0x00000000>;
  1962. lcd_driver_name = "mb709_mipi";
  1963. lcd_backlight = <0x00000032>;
  1964. lcd_if = <0x00000004>;
  1965. lcd_x = <0x00000400>;
  1966. lcd_y = <0x00000258>;
  1967. lcd_width = <0x00000000>;
  1968. lcd_height = <0x00000000>;
  1969. lcd_dclk_freq = <0x00000037>;
  1970. lcd_pwm_used = <0x00000001>;
  1971. lcd_pwm_ch = <0x00000010>;
  1972. lcd_pwm_freq = <0x0000c350>;
  1973. lcd_pwm_pol = <0x00000001>;
  1974. lcd_pwm_max_limit = <0x000000fa>;
  1975. lcd_hbp = <0x00000078>;
  1976. lcd_ht = <0x00000604>;
  1977. lcd_hspw = <0x00000014>;
  1978. lcd_vbp = <0x00000017>;
  1979. lcd_vt = <0x0000027b>;
  1980. lcd_vspw = <0x00000002>;
  1981. lcd_dsi_if = <0x00000002>;
  1982. lcd_dsi_lane = <0x00000004>;
  1983. lcd_dsi_format = <0x00000000>;
  1984. lcd_dsi_eotp = <0x00000000>;
  1985. lcd_dsi_vc = <0x00000000>;
  1986. lcd_dsi_te = <0x00000000>;
  1987. lcd_frm = <0x00000000>;
  1988. lcd_gamma_en = <0x00000000>;
  1989. lcd_bright_curve_en = <0x00000000>;
  1990. lcd_cmap_en = <0x00000000>;
  1991. lcd_bl_en = <0x00000030 0x00000007 0x0000000a 0x00000001 0x00000000 0xffffffff 0x00000001>;
  1992. lcd_bl_en_power = "none";
  1993. lcd_power = "vcc-mipi";
  1994. lcd_fix_power = "vcc-dsi-33";
  1995. lcd_gpio_0 = <0x00000030 0x00000003 0x00000018 0x00000001 0x00000000 0xffffffff 0x00000001>;
  1996. };
  1997. hdmi@01ee0000 {
  1998. compatible = "allwinner,sunxi-hdmi";
  1999. reg = <0x00000000 0x01ee0000 0x00000000 0x00020000>;
  2000. clocks = <0x0000006f 0x00000070>;
  2001. device_type = "hdmi";
  2002. status = "okay";
  2003. hdmi_power = "vcc-hdmi-33";
  2004. hdmi_hdcp_enable = <0x00000000>;
  2005. hdmi_cts_compatibility = <0x00000000>;
  2006. };
  2007. tr@01000000 {
  2008. compatible = "allwinner,sun50i-tr";
  2009. reg = <0x00000000 0x01000000 0x00000000 0x000200bc>;
  2010. interrupts = <0x00000000 0x00000060 0x00000104>;
  2011. clocks = <0x0000006a>;
  2012. status = "okay";
  2013. };
  2014. pwm@01c21400 {
  2015. compatible = "allwinner,sunxi-pwm";
  2016. reg = <0x00000000 0x01c21400 0x00000000 0x0000003c>;
  2017. pwm-number = <0x00000001>;
  2018. pwm-base = <0x00000000>;
  2019. pwms = <0x00000071>;
  2020. };
  2021. pwm0@01c21400 {
  2022. compatible = "allwinner,sunxi-pwm0";
  2023. pinctrl-names = "active", "sleep";
  2024. reg_base = <0x01c21400>;
  2025. reg_busy_offset = <0x00000000>;
  2026. reg_busy_shift = <0x0000001c>;
  2027. reg_enable_offset = <0x00000000>;
  2028. reg_enable_shift = <0x00000004>;
  2029. reg_clk_gating_offset = <0x00000000>;
  2030. reg_clk_gating_shift = <0x00000006>;
  2031. reg_bypass_offset = <0x00000000>;
  2032. reg_bypass_shift = <0x00000009>;
  2033. reg_pulse_start_offset = <0x00000000>;
  2034. reg_pulse_start_shift = <0x00000008>;
  2035. reg_mode_offset = <0x00000000>;
  2036. reg_mode_shift = <0x00000007>;
  2037. reg_polarity_offset = <0x00000000>;
  2038. reg_polarity_shift = <0x00000005>;
  2039. reg_period_offset = <0x00000004>;
  2040. reg_period_shift = <0x00000010>;
  2041. reg_period_width = <0x00000010>;
  2042. reg_active_offset = <0x00000004>;
  2043. reg_active_shift = <0x00000000>;
  2044. reg_active_width = <0x00000010>;
  2045. reg_prescal_offset = <0x00000000>;
  2046. reg_prescal_shift = <0x00000000>;
  2047. reg_prescal_width = <0x00000004>;
  2048. linux,phandle = <0x00000071>;
  2049. phandle = <0x00000071>;
  2050. device_type = "pwm0";
  2051. pwm_used = <0x00000000>;
  2052. pinctrl-0 = <0x000000ad>;
  2053. pinctrl-1 = <0x000000ae>;
  2054. };
  2055. s_pwm@1f03800 {
  2056. compatible = "allwinner,sunxi-s_pwm";
  2057. reg = <0x00000000 0x01f03800 0x00000000 0x0000003c>;
  2058. pwm-number = <0x00000001>;
  2059. pwm-base = <0x00000010>;
  2060. pwms = <0x00000072>;
  2061. };
  2062. spwm0@0x01f03800 {
  2063. compatible = "allwinner,sunxi-pwm16";
  2064. pinctrl-names = "active", "sleep";
  2065. reg_base = <0x01f03800>;
  2066. reg_busy_offset = <0x00000000>;
  2067. reg_busy_shift = <0x0000001c>;
  2068. reg_enable_offset = <0x00000000>;
  2069. reg_enable_shift = <0x00000004>;
  2070. reg_clk_gating_offset = <0x00000000>;
  2071. reg_clk_gating_shift = <0x00000006>;
  2072. reg_bypass_offset = <0x00000000>;
  2073. reg_bypass_shift = <0x00000009>;
  2074. reg_pulse_start_offset = <0x00000000>;
  2075. reg_pulse_start_shift = <0x00000008>;
  2076. reg_mode_offset = <0x00000000>;
  2077. reg_mode_shift = <0x00000007>;
  2078. reg_polarity_offset = <0x00000000>;
  2079. reg_polarity_shift = <0x00000005>;
  2080. reg_period_offset = <0x00000004>;
  2081. reg_period_shift = <0x00000010>;
  2082. reg_period_width = <0x00000010>;
  2083. reg_active_offset = <0x00000004>;
  2084. reg_active_shift = <0x00000000>;
  2085. reg_active_width = <0x00000010>;
  2086. reg_prescal_offset = <0x00000000>;
  2087. reg_prescal_shift = <0x00000000>;
  2088. reg_prescal_width = <0x00000004>;
  2089. linux,phandle = <0x00000072>;
  2090. phandle = <0x00000072>;
  2091. device_type = "spwm0";
  2092. s_pwm_used = <0x00000001>;
  2093. pinctrl-0 = <0x000000af>;
  2094. pinctrl-1 = <0x000000b0>;
  2095. };
  2096. boot_disp {
  2097. compatible = "allwinner,boot_disp";
  2098. device_type = "boot_disp";
  2099. output_disp = <0x00000000>;
  2100. output_type = <0x00000003>;
  2101. output_mode = <0x0000000a>;
  2102. };
  2103. cci@0x01cb3000 {
  2104. compatible = "allwinner,sunxi-csi_cci";
  2105. reg = <0x00000000 0x01cb3000 0x00000000 0x00001000>;
  2106. interrupts = <0x00000000 0x00000055 0x00000004>;
  2107. status = "okay";
  2108. };
  2109. csi_res@0x01cb0000 {
  2110. compatible = "allwinner,sunxi-csi";
  2111. reg = <0x00000000 0x01cb0000 0x00000000 0x00001000>;
  2112. status = "okay";
  2113. };
  2114. vfe@0 {
  2115. device_type = "csi0";
  2116. compatible = "allwinner,sunxi-vfe";
  2117. interrupts = <0x00000000 0x00000054 0x00000004>;
  2118. clocks = <0x00000073 0x00000074 0x00000075 0x00000004 0x00000006 0x00000005>;
  2119. pinctrl-names = "default", "sleep";
  2120. pinctrl-1 = <0x00000077>;
  2121. csi0_sensor_list = <0x00000001>;
  2122. status = "okay";
  2123. pinctrl-0 = <0x000000b1>;
  2124. csi0_mck = <0x00000030 0x00000004 0x00000001 0x00000000 0x00000000 0x00000001 0x00000000>;
  2125. dev@0 {
  2126. csi0_dev0_mname = "hm5065";
  2127. csi0_dev0_twi_addr = <0x0000003e>;
  2128. csi0_dev0_pos = "rear";
  2129. csi0_dev0_isp_used = <0x00000001>;
  2130. csi0_dev0_fmt = <0x00000000>;
  2131. csi0_dev0_stby_mode = <0x00000001>;
  2132. csi0_dev0_vflip = <0x00000000>;
  2133. csi0_dev0_hflip = <0x00000000>;
  2134. csi0_dev0_iovdd = "iovdd-csi";
  2135. csi0_dev0_iovdd_vol = <0x002ab980>;
  2136. csi0_dev0_avdd = "avdd-csi";
  2137. csi0_dev0_avdd_vol = <0x002ab980>;
  2138. csi0_dev0_dvdd = "dvdd-csi-18";
  2139. csi0_dev0_dvdd_vol = <0x001b7740>;
  2140. csi0_dev0_flash_used = <0x00000000>;
  2141. csi0_dev0_flash_type = <0x00000002>;
  2142. csi0_dev0_flvdd = "vdd-csi-led";
  2143. csi0_dev0_flvdd_vol = <0x00325aa0>;
  2144. csi0_dev0_act_used = <0x00000000>;
  2145. csi0_dev0_act_name = "ad5820_act";
  2146. csi0_dev0_act_slave = <0x00000018>;
  2147. status = "okay";
  2148. device_type = "csi0_dev0";
  2149. csi0_dev0_afvdd;
  2150. csi0_dev0_afvdd_vol;
  2151. csi0_dev0_power_en;
  2152. csi0_dev0_reset = <0x00000030 0x00000004 0x0000000e 0x00000000 0x00000000 0x00000001 0x00000000>;
  2153. csi0_dev0_pwdn = <0x00000030 0x00000004 0x0000000f 0x00000000 0x00000000 0x00000001 0x00000000>;
  2154. csi0_dev0_flash_en;
  2155. csi0_dev0_flash_mode;
  2156. csi0_dev0_af_pwdn;
  2157. };
  2158. dev@1 {
  2159. csi0_dev1_mname = "gc2145";
  2160. csi0_dev1_twi_addr = <0x00000078>;
  2161. csi0_dev1_pos = "front";
  2162. csi0_dev1_isp_used = <0x00000001>;
  2163. csi0_dev1_fmt = <0x00000000>;
  2164. csi0_dev1_stby_mode = <0x00000001>;
  2165. csi0_dev1_vflip = <0x00000000>;
  2166. csi0_dev1_hflip = <0x00000000>;
  2167. csi0_dev1_iovdd = "iovdd-csi";
  2168. csi0_dev1_iovdd_vol = <0x002ab980>;
  2169. csi0_dev1_avdd = "avdd-csi";
  2170. csi0_dev1_avdd_vol = <0x002ab980>;
  2171. csi0_dev1_dvdd = "dvdd-csi-18";
  2172. csi0_dev1_dvdd_vol = <0x001b7740>;
  2173. csi0_dev1_flash_used = <0x00000000>;
  2174. csi0_dev1_flash_type = <0x00000002>;
  2175. csi0_dev1_flvdd = "vdd-csi-led";
  2176. csi0_dev1_flvdd_vol = <0x00325aa0>;
  2177. csi0_dev1_act_used = <0x00000000>;
  2178. csi0_dev1_act_name = "ad5820_act";
  2179. csi0_dev1_act_slave = <0x00000018>;
  2180. status = "okay";
  2181. device_type = "csi0_dev1";
  2182. csi0_dev1_afvdd;
  2183. csi0_dev1_afvdd_vol;
  2184. csi0_dev1_power_en;
  2185. csi0_dev1_reset = <0x00000030 0x00000004 0x00000010 0x00000000 0x00000000 0x00000001 0x00000000>;
  2186. csi0_dev1_pwdn = <0x00000030 0x00000004 0x00000011 0x00000000 0x00000000 0x00000001 0x00000000>;
  2187. csi0_dev1_flash_en;
  2188. csi0_dev1_flash_mode;
  2189. csi0_dev1_af_pwdn;
  2190. };
  2191. };
  2192. vdevice@0 {
  2193. compatible = "allwinner,sun50i-vdevice";
  2194. pinctrl-names = "default";
  2195. test-gpios = <0x00000079 0x0000000b 0x00000000 0x00000001 0x00000002 0x00000003 0x00000004>;
  2196. status = "okay";
  2197. device_type = "Vdevice";
  2198. pinctrl-0 = <0x000000b9>;
  2199. };
  2200. ce@1c15000 {
  2201. compatible = "allwinner,sunxi-ce";
  2202. reg = <0x00000000 0x01c15000 0x00000000 0x00000080 0x00000000 0x01c15800 0x00000000 0x00000080>;
  2203. interrupts = <0x00000000 0x0000005e 0x0000ff01 0x00000000 0x00000050 0x0000ff01>;
  2204. clock-frequency = <0x11e1a300 0x0bebc200>;
  2205. clocks = <0x0000007a 0x0000007b>;
  2206. };
  2207. deinterlace@0x01e00000 {
  2208. #address-cells = <0x00000001>;
  2209. #size-cells = <0x00000000>;
  2210. compatible = "allwinner,sunxi-deinterlace";
  2211. reg = <0x00000000 0x01e00000 0x00000000 0x0000077c>;
  2212. interrupts = <0x00000000 0x0000005d 0x00000004>;
  2213. clocks = <0x0000007c 0x00000004>;
  2214. status = "okay";
  2215. device_type = "di";
  2216. };
  2217. smartcard@0x01c2c400 {
  2218. #address-cells = <0x00000001>;
  2219. #size-cells = <0x00000000>;
  2220. compatible = "allwinner,sunxi-scr";
  2221. reg = <0x00000000 0x01c2c400 0x00000000 0x00000100>;
  2222. interrupts = <0x00000000 0x00000053 0x00000004>;
  2223. clocks = <0x0000007d 0x0000007e>;
  2224. clock-frequency = <0x016e3600>;
  2225. pinctrl-names = "default";
  2226. pinctrl-0 = <0x0000007f>;
  2227. status = "okay";
  2228. device_type = "smc";
  2229. smc_used;
  2230. smc_rst;
  2231. smc_vppen;
  2232. smc_vppp;
  2233. smc_det;
  2234. smc_vccen;
  2235. smc_sck;
  2236. smc_sda;
  2237. };
  2238. nmi@0x01f00c00 {
  2239. #address-cells = <0x00000001>;
  2240. #size-cells = <0x00000000>;
  2241. compatible = "allwinner,sunxi-nmi";
  2242. reg = <0x00000000 0x01f00c00 0x00000000 0x00000050>;
  2243. nmi_irq_ctrl = <0x0000000c>;
  2244. nmi_irq_en = <0x00000040>;
  2245. nmi_irq_status = <0x00000010>;
  2246. nmi_irq_mask = <0x00000050>;
  2247. status = "okay";
  2248. };
  2249. pmu0@0 {
  2250. compatible = "allwinner,pmu0";
  2251. device_type = "pmu0";
  2252. pmu_batdeten = <0x00000001>;
  2253. pmu_init_chgend_rate = <0x00000014>;
  2254. pmu_init_chg_enabled = <0x00000001>;
  2255. pmu_init_adc_freq = <0x00000320>;
  2256. pmu_init_adcts_freq = <0x00000320>;
  2257. pmu_init_chg_pretime = <0x00000046>;
  2258. pmu_init_chg_csttime = <0x000002d0>;
  2259. pmu_batt_cap_correct = <0x00000001>;
  2260. pmu_chg_end_on_en = <0x00000000>;
  2261. pmu_pwroff_vol = <0x00000ce4>;
  2262. pmu_pwron_vol = <0x00000a28>;
  2263. pmu_powkey_off_delay_time = <0x00000000>;
  2264. pmu_pwrok_time = <0x00000040>;
  2265. pmu_reset_shutdown_en = <0x00000001>;
  2266. pmu_restvol_adjust_time = <0x0000003c>;
  2267. pmu_ocv_cou_adjust_time = <0x0000003c>;
  2268. pmu_vbusen_func = <0x00000001>;
  2269. pmu_reset = <0x00000000>;
  2270. pmu_IRQ_wakeup = <0x00000001>;
  2271. pmu_hot_shutdowm = <0x00000001>;
  2272. pmu_inshort = <0x00000000>;
  2273. pmu_bat_shutdown_ltf = <0x00000c80>;
  2274. pmu_bat_shutdown_htf = <0x000000ed>;
  2275. status = "okay";
  2276. pmu_id = <0x00000006>;
  2277. pmu_twi_addr = <0x00000034>;
  2278. pmu_twi_id = <0x00000001>;
  2279. pmu_irq_id = <0x00000040>;
  2280. pmu_chg_ic_temp = <0x00000000>;
  2281. pmu_battery_rdc = <0x00000058>;
  2282. pmu_battery_cap = <0x000012c0>;
  2283. pmu_runtime_chgcur = <0x000001c2>;
  2284. pmu_suspend_chgcur = <0x000005dc>;
  2285. pmu_shutdown_chgcur = <0x000005dc>;
  2286. pmu_init_chgvol = <0x00001068>;
  2287. pmu_ac_vol = <0x00000fa0>;
  2288. pmu_ac_cur = <0x00000dac>;
  2289. pmu_usbpc_vol = <0x00001130>;
  2290. pmu_usbpc_cur = <0x000001f4>;
  2291. pmu_battery_warning_level1 = <0x0000000f>;
  2292. pmu_battery_warning_level2 = <0x00000000>;
  2293. pmu_chgled_func = <0x00000000>;
  2294. pmu_chgled_type = <0x00000000>;
  2295. pmu_bat_para1 = <0x00000000>;
  2296. pmu_bat_para2 = <0x00000000>;
  2297. pmu_bat_para3 = <0x00000000>;
  2298. pmu_bat_para4 = <0x00000000>;
  2299. pmu_bat_para5 = <0x00000000>;
  2300. pmu_bat_para6 = <0x00000000>;
  2301. pmu_bat_para7 = <0x00000001>;
  2302. pmu_bat_para8 = <0x00000001>;
  2303. pmu_bat_para9 = <0x00000002>;
  2304. pmu_bat_para10 = <0x00000003>;
  2305. pmu_bat_para11 = <0x00000004>;
  2306. pmu_bat_para12 = <0x0000000a>;
  2307. pmu_bat_para13 = <0x00000011>;
  2308. pmu_bat_para14 = <0x0000001a>;
  2309. pmu_bat_para15 = <0x00000029>;
  2310. pmu_bat_para16 = <0x0000002e>;
  2311. pmu_bat_para17 = <0x00000033>;
  2312. pmu_bat_para18 = <0x00000038>;
  2313. pmu_bat_para19 = <0x0000003b>;
  2314. pmu_bat_para20 = <0x00000041>;
  2315. pmu_bat_para21 = <0x00000045>;
  2316. pmu_bat_para22 = <0x0000004b>;
  2317. pmu_bat_para23 = <0x0000004f>;
  2318. pmu_bat_para24 = <0x00000053>;
  2319. pmu_bat_para25 = <0x00000059>;
  2320. pmu_bat_para26 = <0x0000005f>;
  2321. pmu_bat_para27 = <0x00000062>;
  2322. pmu_bat_para28 = <0x00000064>;
  2323. pmu_bat_para29 = <0x00000064>;
  2324. pmu_bat_para30 = <0x00000064>;
  2325. pmu_bat_para31 = <0x00000064>;
  2326. pmu_bat_para32 = <0x00000064>;
  2327. pmu_bat_temp_enable = <0x00000001>;
  2328. pmu_bat_charge_ltf = <0x000008d5>;
  2329. pmu_bat_charge_htf = <0x00000184>;
  2330. pmu_bat_temp_para1 = <0x00001d2a>;
  2331. pmu_bat_temp_para2 = <0x00001180>;
  2332. pmu_bat_temp_para3 = <0x00000dbe>;
  2333. pmu_bat_temp_para4 = <0x00000ae2>;
  2334. pmu_bat_temp_para5 = <0x000008af>;
  2335. pmu_bat_temp_para6 = <0x000006fc>;
  2336. pmu_bat_temp_para7 = <0x000005a8>;
  2337. pmu_bat_temp_para8 = <0x000003c9>;
  2338. pmu_bat_temp_para9 = <0x00000298>;
  2339. pmu_bat_temp_para10 = <0x000001d2>;
  2340. pmu_bat_temp_para11 = <0x00000189>;
  2341. pmu_bat_temp_para12 = <0x0000014d>;
  2342. pmu_bat_temp_para13 = <0x0000011b>;
  2343. pmu_bat_temp_para14 = <0x000000f2>;
  2344. pmu_bat_temp_para15 = <0x000000b3>;
  2345. pmu_bat_temp_para16 = <0x00000086>;
  2346. pmu_powkey_off_time = <0x00001770>;
  2347. pmu_powkey_off_func = <0x00000000>;
  2348. pmu_powkey_off_en = <0x00000001>;
  2349. pmu_powkey_long_time = <0x000005dc>;
  2350. pmu_powkey_on_time = <0x000003e8>;
  2351. power_start = <0x00000000>;
  2352. };
  2353. regu@0 {
  2354. compatible = "allwinner,pmu0_regu";
  2355. regulator_count = <0x00000017>;
  2356. status = "okay";
  2357. device_type = "pmu0_regu";
  2358. regulator1 = "axp81x_dcdc1 none vcc-nand vcc-emmc vcc-sdc vcc-usb-30 vcc-io vcc-pd";
  2359. regulator2 = "axp81x_dcdc2 none vdd-cpua";
  2360. regulator3 = "axp81x_dcdc3 none";
  2361. regulator4 = "axp81x_dcdc4 none";
  2362. regulator5 = "axp81x_dcdc5 none vcc-dram";
  2363. regulator6 = "axp81x_dcdc6 none vdd-sys";
  2364. regulator7 = "axp81x_dcdc7 none";
  2365. regulator8 = "axp81x_rtc none";
  2366. regulator9 = "axp81x_aldo1 none vdd-csi-led iovdd-csi vcc-pe";
  2367. regulator10 = "axp81x_aldo2 none vcc-pl";
  2368. regulator11 = "axp81x_aldo3 none vcc-avcc vcc-pll";
  2369. regulator12 = "axp81x_dldo1 none vcc-hdmi-33";
  2370. regulator13 = "axp81x_dldo2 none vcc-mipi";
  2371. regulator14 = "axp81x_dldo3 none avdd-csi";
  2372. regulator15 = "axp81x_dldo4 none vcc-deviceio";
  2373. regulator16 = "axp81x_eldo1 none vcc-cpvdd vcc-wifi-io vcc-pc vcc-pg";
  2374. regulator17 = "axp81x_eldo2 none vcc-lcd-0";
  2375. regulator18 = "axp81x_eldo3 none dvdd-csi-18";
  2376. regulator19 = "axp81x_fldo1 none vcc-hsic-12";
  2377. regulator20 = "axp81x_fldo2 none vdd-cpus";
  2378. regulator21 = "axp81x_gpio0ldo none vcc-ctp";
  2379. regulator22 = "axp81x_gpio1ldo none";
  2380. regulator23 = "axp81x_dc1sw none vcc-lvds vcc-dsi-33";
  2381. };
  2382. nand0@01c03000 {
  2383. compatible = "allwinner,sun50i-nand";
  2384. device_type = "nand0";
  2385. reg = <0x00000000 0x01c03000 0x00000000 0x00001000>;
  2386. interrupts = <0x00000000 0x00000046 0x00000004>;
  2387. clocks = <0x00000004 0x00000080>;
  2388. pinctrl-names = "default", "sleep";
  2389. pinctrl-1 = <0x00000083>;
  2390. nand0_regulator1 = "vcc-nand";
  2391. nand0_regulator2 = "none";
  2392. nand0_cache_level = <0x55aaaa55>;
  2393. nand0_flush_cache_num = <0x55aaaa55>;
  2394. nand0_capacity_level = <0x55aaaa55>;
  2395. nand0_id_number_ctl = <0x55aaaa55>;
  2396. nand0_print_level = <0x55aaaa55>;
  2397. nand0_p0 = <0x55aaaa55>;
  2398. nand0_p1 = <0x55aaaa55>;
  2399. nand0_p2 = <0x55aaaa55>;
  2400. nand0_p3 = <0x55aaaa55>;
  2401. status = "disabled";
  2402. nand0_support_2ch = <0x00000000>;
  2403. pinctrl-0 = <0x000000ab 0x000000ac>;
  2404. };
  2405. thermal_sensor {
  2406. compatible = "allwinner,thermal_sensor";
  2407. reg = <0x00000000 0x01c25000 0x00000000 0x00000400>;
  2408. interrupts = <0x00000000 0x0000001f 0x00000000>;
  2409. clocks = <0x00000006 0x00000084>;
  2410. sensor_num = <0x00000003>;
  2411. shut_temp = <0x00000078>;
  2412. status = "okay";
  2413. combine0 {
  2414. #thermal-sensor-cells = <0x00000001>;
  2415. combine_cnt = <0x00000003>;
  2416. combine_type = "max";
  2417. combine_chn = <0x00000000 0x00000001 0x00000002>;
  2418. linux,phandle = <0x00000085>;
  2419. phandle = <0x00000085>;
  2420. };
  2421. };
  2422. cpu_budget_cool {
  2423. compatible = "allwinner,budget_cooling";
  2424. #cooling-cells = <0x00000002>;
  2425. status = "okay";
  2426. state_cnt = <0x0000000e>;
  2427. cluster_num = <0x00000001>;
  2428. state0 = <0x00148200 0x00000004>;
  2429. state1 = <0x0013C680 0x00000004>;
  2430. state2 = <0x00130B00 0x00000004>;
  2431. state3 = <0x00124f80 0x00000004>;
  2432. state4 = <0x00119400 0x00000004>;
  2433. state5 = <0x0010d880 0x00000004>;
  2434. state6 = <0x00101d00 0x00000004>;
  2435. state7 = <0x000f6180 0x00000004>;
  2436. state8 = <0x000ea600 0x00000004>;
  2437. state9 = <0x000dea80 0x00000004>;
  2438. state10 = <0x000c7380 0x00000004>;
  2439. state11 = <0x0009e340 0x00000004>;
  2440. state12 = <0x0009e340 0x00000002>;
  2441. state13 = <0x0009e340 0x00000001>;
  2442. linux,phandle = <0x00000087>;
  2443. phandle = <0x00000087>;
  2444. };
  2445. gpu_cooling {
  2446. compatible = "allwinner,gpu_cooling";
  2447. reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
  2448. #cooling-cells = <0x00000002>;
  2449. status = "okay";
  2450. state_cnt = <0x00000003>;
  2451. state0 = <0x00000000>;
  2452. state1 = <0x00000168>;
  2453. state2 = <0x00000090>;
  2454. linux,phandle = <0x0000008c>;
  2455. phandle = <0x0000008c>;
  2456. };
  2457. thermal-zones {
  2458. soc_thermal {
  2459. polling-delay-passive = <0x000001f4>;
  2460. polling-delay = <0x000007d0>;
  2461. thermal-sensors = <0x00000085 0x00000000>;
  2462. trips {
  2463. t0 {
  2464. temperature = <85>;
  2465. type = "passive";
  2466. hysteresis = <0x00000000>;
  2467. linux,phandle = <0x00000086>;
  2468. phandle = <0x00000086>;
  2469. };
  2470. t1 {
  2471. temperature = <90>;
  2472. type = "passive";
  2473. hysteresis = <0x00000000>;
  2474. linux,phandle = <0x00000088>;
  2475. phandle = <0x00000088>;
  2476. };
  2477. t2 {
  2478. temperature = <95>;
  2479. type = "passive";
  2480. hysteresis = <0x00000000>;
  2481. linux,phandle = <0x00000089>;
  2482. phandle = <0x00000089>;
  2483. };
  2484. t3 {
  2485. temperature = <100>;
  2486. type = "passive";
  2487. hysteresis = <0x00000000>;
  2488. linux,phandle = <0x0000008a>;
  2489. phandle = <0x0000008a>;
  2490. };
  2491. t4 {
  2492. temperature = <90>;
  2493. type = "passive";
  2494. hysteresis = <0x00000000>;
  2495. linux,phandle = <0x0000008b>;
  2496. phandle = <0x0000008b>;
  2497. };
  2498. t5 {
  2499. temperature = <95>;
  2500. type = "passive";
  2501. hysteresis = <0x00000000>;
  2502. linux,phandle = <0x0000008d>;
  2503. phandle = <0x0000008d>;
  2504. };
  2505. t6 {
  2506. temperature = <105>;
  2507. type = "critical";
  2508. hysteresis = <0x00000000>;
  2509. };
  2510. };
  2511. cooling-maps {
  2512. bind0 {
  2513. contribution = <0x00000000>;
  2514. trip = <0x00000086>;
  2515. cooling-device = <0x00000087 0x00000001 0x00000001>;
  2516. };
  2517. bind1 {
  2518. contribution = <0x00000000>;
  2519. trip = <0x00000088>;
  2520. cooling-device = <0x00000087 0x00000002 0x00000002>;
  2521. };
  2522. bind2 {
  2523. contribution = <0x00000000>;
  2524. trip = <0x00000089>;
  2525. cooling-device = <0x00000087 0x00000003 0x00000006>;
  2526. };
  2527. bind3 {
  2528. contribution = <0x00000000>;
  2529. trip = <0x0000008a>;
  2530. cooling-device = <0x00000087 0x00000007 0x00000009>;
  2531. };
  2532. bind4 {
  2533. contribution = <0x00000000>;
  2534. trip = <0x0000008b>;
  2535. cooling-device = <0x0000008c 0x00000001 0x00000001>;
  2536. };
  2537. bind5 {
  2538. contribution = <0x00000000>;
  2539. trip = <0x0000008d>;
  2540. cooling-device = <0x0000008c 0x00000002 0x00000002>;
  2541. };
  2542. };
  2543. };
  2544. };
  2545. keyboard {
  2546. compatible = "allwinner,keyboard_2000mv";
  2547. reg = <0x00000000 0x01c21800 0x00000000 0x00000400>;
  2548. interrupts = <0x00000000 0x0000001e 0x00000000>;
  2549. status = "okay";
  2550. key_cnt = <0x00000005>;
  2551. key1 = <0x000000f0 0x00000073>;
  2552. key2 = <0x000001f4 0x00000072>;
  2553. key3 = <0x000002bc 0x0000008b>;
  2554. key4 = <0x0000037a 0x0000001c>;
  2555. key5 = <0x000007d0 0x00000066>;
  2556. };
  2557. eth@01c30000 {
  2558. compatible = "allwinner,sunxi-gmac";
  2559. reg = <0x00000000 0x01c30000 0x00000000 0x00040000 0x00000000 0x01c00000 0x00000000 0x00000030>;
  2560. pinctrl-names = "default";
  2561. interrupts = <0x00000000 0x00000052 0x00000004>;
  2562. interrupt-names = "gmacirq";
  2563. clocks = <0x0000008f>;
  2564. clock-names = "gmac";
  2565. phy-mode = "rgmii";
  2566. tx-delay = <0x00000003>;
  2567. rx-delay = <0x00000000>;
  2568. gmac_power1 = "axp81x_dc1sw:0";
  2569. status = "okay";
  2570. device_type = "gmac0";
  2571. pinctrl-0 = <0x0000009e>;
  2572. gmac_power2;
  2573. gmac_power3;
  2574. };
  2575. product {
  2576. device_type = "product";
  2577. version = "100";
  2578. machine = "evb";
  2579. };
  2580. platform {
  2581. device_type = "platform";
  2582. eraseflag = <0x00000001>;
  2583. };
  2584. target {
  2585. device_type = "target";
  2586. boot_clock = <0x000003f0>;
  2587. storage_type = <0xffffffff>;
  2588. burn_key = <0x00000000>;
  2589. };
  2590. power_sply {
  2591. device_type = "power_sply";
  2592. dcdc1_vol = <0x000f4f24>;
  2593. dcdc2_vol = <0x000f468c>;
  2594. dcdc6_vol = <0x000f468c>;
  2595. aldo1_vol = <0x00000af0>;
  2596. aldo2_vol = <0x000f4948>;
  2597. aldo3_vol = <0x000f4df8>;
  2598. dldo1_vol = <0x00000ce4>;
  2599. dldo2_vol = <0x00000ce4>;
  2600. dldo3_vol = <0x00000af0>;
  2601. dldo4_vol = <0x000f4f24>;
  2602. eldo1_vol = <0x000f4948>;
  2603. eldo2_vol = <0x00000708>;
  2604. eldo3_vol = <0x00000708>;
  2605. fldo1_vol = <0x000004b0>;
  2606. fldo2_vol = <0x000f468c>;
  2607. gpio0_vol = <0x00000c1c>;
  2608. };
  2609. card_boot {
  2610. device_type = "card_boot";
  2611. logical_start = <0x0000a000>;
  2612. sprite_gpio0;
  2613. };
  2614. pm_para {
  2615. device_type = "pm_para";
  2616. standby_mode = <0x00000001>;
  2617. };
  2618. card0_boot_para {
  2619. device_type = "card0_boot_para";
  2620. card_ctrl = <0x00000000>;
  2621. card_high_speed = <0x00000001>;
  2622. card_line = <0x00000004>;
  2623. pinctrl-0 = <0x00000099>;
  2624. };
  2625. card2_boot_para {
  2626. device_type = "card2_boot_para";
  2627. sdc_io_1v8 = <0x00000001>;
  2628. card_ctrl = <0x00000002>;
  2629. card_high_speed = <0x00000001>;
  2630. card_line = <0x00000008>;
  2631. pinctrl-0 = <0x0000009a>;
  2632. sdc_ex_dly_used = <0x00000002>;
  2633. };
  2634. twi_para {
  2635. device_type = "twi_para";
  2636. twi_port = <0x00000000>;
  2637. pinctrl-0 = <0x0000009b>;
  2638. };
  2639. uart_para {
  2640. device_type = "uart_para";
  2641. uart_debug_port = <0x00000000>;
  2642. pinctrl-0 = <0x0000009c>;
  2643. };
  2644. jtag_para {
  2645. device_type = "jtag_para";
  2646. jtag_enable = <0x00000001>;
  2647. pinctrl-0 = <0x0000009d>;
  2648. };
  2649. clock {
  2650. device_type = "clock";
  2651. pll4 = <0x0000012c>;
  2652. pll6 = <0x00000258>;
  2653. pll8 = <0x00000168>;
  2654. pll9 = <0x00000129>;
  2655. pll10 = <0x00000108>;
  2656. };
  2657. rtp_para {
  2658. device_type = "rtp_para";
  2659. rtp_used = <0x00000000>;
  2660. rtp_screen_size = <0x00000005>;
  2661. rtp_regidity_level = <0x00000005>;
  2662. rtp_press_threshold_enable = <0x00000000>;
  2663. rtp_press_threshold = <0x00001f40>;
  2664. rtp_sensitive_level = <0x0000000f>;
  2665. rtp_exchange_x_y_flag = <0x00000000>;
  2666. };
  2667. ctp {
  2668. device_type = "ctp";
  2669. compatible = "allwinner,sun50i-ctp-para";
  2670. status = "disabled";
  2671. ctp_name = "gt911_DB";
  2672. ctp_twi_id = <0x00000000>;
  2673. ctp_twi_addr = <0x00000040>;
  2674. ctp_screen_max_x = <0x00000400>;
  2675. ctp_screen_max_y = <0x00000258>;
  2676. ctp_revert_x_flag = <0x00000001>;
  2677. ctp_revert_y_flag = <0x00000001>;
  2678. ctp_exchange_x_y_flag = <0x00000000>;
  2679. ctp_int_port = <0x00000030 0x00000007 0x00000004 0x00000006 0xffffffff 0xffffffff 0xffffffff>;
  2680. ctp_wakeup = <0x00000030 0x00000007 0x0000000b 0x00000001 0xffffffff 0xffffffff 0x00000001>;
  2681. ctp_power_ldo = "vcc-ctp";
  2682. ctp_power_ldo_vol = <0x00000ce4>;
  2683. ctp_power_io;
  2684. };
  2685. ctp_list {
  2686. device_type = "ctp_list";
  2687. compatible = "allwinner,sun50i-ctp-list";
  2688. status = "okay";
  2689. gslX680new = <0x00000001>;
  2690. gt9xx_ts = <0x00000000>;
  2691. gt9xxf_ts = <0x00000001>;
  2692. gt9xxnew_ts = <0x00000000>;
  2693. gt82x = <0x00000001>;
  2694. zet622x = <0x00000001>;
  2695. aw5306_ts = <0x00000001>;
  2696. };
  2697. tkey_para {
  2698. device_type = "tkey_para";
  2699. tkey_used = <0x00000000>;
  2700. tkey_twi_id;
  2701. tkey_twi_addr;
  2702. tkey_int;
  2703. };
  2704. motor_para {
  2705. device_type = "motor_para";
  2706. motor_used = <0x00000000>;
  2707. motor_shake = <0x00000031 0x0000fffe 0x00000003 0x00000001 0xffffffff 0xffffffff 0x00000001>;
  2708. };
  2709. tvout_para {
  2710. device_type = "tvout_para";
  2711. tvout_used;
  2712. tvout_channel_num;
  2713. tv_en;
  2714. };
  2715. tvin_para {
  2716. device_type = "tvin_para";
  2717. tvin_used;
  2718. tvin_channel_num;
  2719. };
  2720. serial_feature {
  2721. device_type = "serial_feature";
  2722. sn_filename = "sn.txt";
  2723. };
  2724. gsensor {
  2725. device_type = "gsensor";
  2726. compatible = "allwinner,sun50i-gsensor-para";
  2727. status = "okay";
  2728. gsensor_twi_id = <0x00000001>;
  2729. gsensor_twi_addr = <0x0000001d>;
  2730. gsensor_vcc_io = "vcc-deviceio";
  2731. gsensor_vcc_io_val = <0x00000ce4>;
  2732. gsensor_int1 = <0x00000030 0x00000007 0x00000005 0x00000006 0x00000001 0xffffffff 0xffffffff>;
  2733. gsensor_int2 = <0x00000030 0x00000007 0x00000006 0x00000006 0x00000001 0xffffffff 0xffffffff>;
  2734. };
  2735. gsensor_list {
  2736. device_type = "gsensor_list";
  2737. compatible = "allwinner,sun50i-gsensor-list-para";
  2738. gsensor_list__used = <0x00000001>;
  2739. lsm9ds0_acc_mag = <0x00000001>;
  2740. bma250 = <0x00000001>;
  2741. mma8452 = <0x00000001>;
  2742. mma7660 = <0x00000001>;
  2743. mma865x = <0x00000001>;
  2744. afa750 = <0x00000001>;
  2745. lis3de_acc = <0x00000001>;
  2746. lis3dh_acc = <0x00000001>;
  2747. kxtik = <0x00000001>;
  2748. dmard10 = <0x00000000>;
  2749. dmard06 = <0x00000001>;
  2750. mxc622x = <0x00000001>;
  2751. fxos8700 = <0x00000001>;
  2752. lsm303d = <0x00000000>;
  2753. sc7a30 = <0x00000001>;
  2754. };
  2755. 3g_para {
  2756. device_type = "3g_para";
  2757. 3g_used = <0x00000000>;
  2758. 3g_usbc_num = <0x00000002>;
  2759. 3g_uart_num = <0x00000000>;
  2760. bb_vbat = <0x00000079 0x0000000b 0x00000003 0x00000001 0xffffffff 0xffffffff 0x00000000>;
  2761. bb_host_wake = <0x00000079 0x0000000c 0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000000>;
  2762. bb_on = <0x00000079 0x0000000c 0x00000001 0x00000001 0xffffffff 0xffffffff 0x00000000>;
  2763. bb_pwr_on = <0x00000079 0x0000000c 0x00000003 0x00000001 0xffffffff 0xffffffff 0x00000000>;
  2764. bb_wake = <0x00000079 0x0000000c 0x00000004 0x00000001 0xffffffff 0xffffffff 0x00000000>;
  2765. bb_rf_dis = <0x00000079 0x0000000c 0x00000005 0x00000001 0xffffffff 0xffffffff 0x00000000>;
  2766. bb_rst = <0x00000079 0x0000000c 0x00000006 0x00000001 0xffffffff 0xffffffff 0x00000000>;
  2767. 3g_int;
  2768. };
  2769. gyroscopesensor {
  2770. device_type = "gyroscopesensor";
  2771. compatible = "allwinner,sun50i-gyr_sensors-para";
  2772. status = "disabled";
  2773. gy_twi_id = <0x00000002>;
  2774. gy_twi_addr = <0x0000006a>;
  2775. gy_int1 = <0x00000030 0x00000000 0x0000000a 0x00000006 0x00000001 0xffffffff 0xffffffff>;
  2776. gy_int2;
  2777. };
  2778. gy_list {
  2779. device_type = "gy_list";
  2780. compatible = "allwinner,sun50i-gyr_sensors-list-para";
  2781. status = "disabled";
  2782. lsm9ds0_gyr = <0x00000001>;
  2783. l3gd20_gyr = <0x00000000>;
  2784. bmg160_gyr = <0x00000001>;
  2785. };
  2786. lightsensor {
  2787. device_type = "lightsensor";
  2788. compatible = "allwinner,sun50i-lsensors-para";
  2789. status = "disabled";
  2790. ls_twi_id = <0x00000002>;
  2791. ls_twi_addr = <0x00000023>;
  2792. ls_int = <0x00000030 0x00000000 0x0000000c 0x00000006 0x00000001 0xffffffff 0xffffffff>;
  2793. };
  2794. ls_list {
  2795. device_type = "ls_list";
  2796. compatible = "allwinner,sun50i-lsensors-list-para";
  2797. status = "disabled";
  2798. ltr_501als = <0x00000001>;
  2799. jsa1212 = <0x00000000>;
  2800. jsa1127 = <0x00000001>;
  2801. stk3x1x = <0x00000000>;
  2802. };
  2803. compasssensor {
  2804. device_type = "compasssensor";
  2805. compatible = "allwinner,sun50i-compass-para";
  2806. status = "disabled";
  2807. compass_twi_id = <0x00000002>;
  2808. compass_twi_addr = <0x0000000d>;
  2809. compass_int = <0x00000030 0x00000000 0x0000000b 0x00000006 0x00000001 0xffffffff 0xffffffff>;
  2810. };
  2811. compass_list {
  2812. device_type = "compass_list";
  2813. compatible = "allwinner,sun50i-compass-list-para";
  2814. status = "disabled";
  2815. lsm9ds0 = <0x00000001>;
  2816. lsm303d = <0x00000000>;
  2817. };
  2818. recovery_key {
  2819. device_type = "recovery_key";
  2820. key_max = <0x0000000c>;
  2821. key_min = <0x0000000a>;
  2822. };
  2823. fastboot_key {
  2824. device_type = "fastboot_key";
  2825. key_max = <0x00000006>;
  2826. key_min = <0x00000004>;
  2827. };
  2828. };
  2829. aliases {
  2830. serial0 = "/soc@01c00000/uart@01c28000";
  2831. serial1 = "/soc@01c00000/uart@01c28400";
  2832. serial2 = "/soc@01c00000/uart@01c28800";
  2833. serial3 = "/soc@01c00000/uart@01c28c00";
  2834. serial4 = "/soc@01c00000/uart@01c29000";
  2835. twi0 = "/soc@01c00000/twi@0x01c2ac00";
  2836. twi1 = "/soc@01c00000/twi@0x01c2b000";
  2837. twi2 = "/soc@01c00000/twi@0x01c2b400";
  2838. spi0 = "/soc@01c00000/spi@01c68000";
  2839. spi1 = "/soc@01c00000/spi@01c69000";
  2840. global_timer0 = "/soc@01c00000/timer@1c20c00";
  2841. cci0 = "/soc@01c00000/cci@0x01cb3000";
  2842. csi_res0 = "/soc@01c00000/csi_res@0x01cb0000";
  2843. vfe0 = "/soc@01c00000/vfe@0";
  2844. mmc0 = "/soc@01c00000/sdmmc@01c0f000";
  2845. mmc2 = "/soc@01c00000/sdmmc@01C11000";
  2846. nand0 = "/soc@01c00000/nand0@01c03000";
  2847. disp = "/soc@01c00000/disp@01000000";
  2848. lcd0 = "/soc@01c00000/lcd0@01c0c000";
  2849. hdmi = "/soc@01c00000/hdmi@01ee0000";
  2850. pwm = "/soc@01c00000/pwm@01c21400";
  2851. pwm0 = "/soc@01c00000/pwm0@01c21400";
  2852. s_pwm = "/soc@01c00000/s_pwm@1f03800";
  2853. spwm0 = "/soc@01c00000/spwm0@0x01f03800";
  2854. boot_disp = "/soc@01c00000/boot_disp";
  2855. };
  2856. chosen {
  2857. bootargs = "earlyprintk=sunxi-uart,0x01c28000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init";
  2858. linux,initrd-start = <0x00000000 0x00000000>;
  2859. linux,initrd-end = <0x00000000 0x00000000>;
  2860. };
  2861. cpus {
  2862. #address-cells = <0x00000002>;
  2863. #size-cells = <0x00000000>;
  2864. cpu@0 {
  2865. device_type = "cpu";
  2866. compatible = "arm,cortex-a53", "arm,armv8";
  2867. reg = <0x00000000 0x00000000>;
  2868. enable-method = "psci";
  2869. cpufreq_tbl = <0x00075300 0x000927c0 0x000afc80 0x000c7380 0x000dea80 0x000ea600 0x000f6180 0x00101d00 0x0010d880 0x00119400 0x00124f80 0x00130B00 0x0013C680 0x00148200>;
  2870. clock-latency = <0x001e8480>;
  2871. clock-frequency = <0x3c14dc00>;
  2872. cpu-idle-states = <0x00000090 0x00000091 0x00000092>;
  2873. };
  2874. cpu@1 {
  2875. device_type = "cpu";
  2876. compatible = "arm,cortex-a53", "arm,armv8";
  2877. reg = <0x00000000 0x00000001>;
  2878. enable-method = "psci";
  2879. clock-frequency = <0x3c14dc00>;
  2880. cpu-idle-states = <0x00000090 0x00000091 0x00000092>;
  2881. };
  2882. cpu@2 {
  2883. device_type = "cpu";
  2884. compatible = "arm,cortex-a53", "arm,armv8";
  2885. reg = <0x00000000 0x00000002>;
  2886. enable-method = "psci";
  2887. clock-frequency = <0x3c14dc00>;
  2888. cpu-idle-states = <0x00000090 0x00000091 0x00000092>;
  2889. };
  2890. cpu@3 {
  2891. device_type = "cpu";
  2892. compatible = "arm,cortex-a53", "arm,armv8";
  2893. reg = <0x00000000 0x00000003>;
  2894. enable-method = "psci";
  2895. clock-frequency = <0x3c14dc00>;
  2896. cpu-idle-states = <0x00000090 0x00000091 0x00000092>;
  2897. };
  2898. idle-states {
  2899. entry-method = "arm,psci";
  2900. cpu-sleep-0 {
  2901. compatible = "arm,idle-state";
  2902. arm,psci-suspend-param = <0x00010000>;
  2903. entry-latency-us = <0x00000028>;
  2904. exit-latency-us = <0x00000064>;
  2905. min-residency-us = <0x00000096>;
  2906. linux,phandle = <0x00000090>;
  2907. phandle = <0x00000090>;
  2908. };
  2909. cluster-sleep-0 {
  2910. compatible = "arm,idle-state";
  2911. arm,psci-suspend-param = <0x01010000>;
  2912. entry-latency-us = <0x000001f4>;
  2913. exit-latency-us = <0x000003e8>;
  2914. min-residency-us = <0x000009c4>;
  2915. linux,phandle = <0x00000091>;
  2916. phandle = <0x00000091>;
  2917. };
  2918. sys-sleep-0 {
  2919. compatible = "arm,idle-state";
  2920. arm,psci-suspend-param = <0x02010000>;
  2921. entry-latency-us = <0x000003e8>;
  2922. exit-latency-us = <0x000007d0>;
  2923. min-residency-us = <0x00001194>;
  2924. linux,phandle = <0x00000092>;
  2925. phandle = <0x00000092>;
  2926. };
  2927. };
  2928. };
  2929. psci {
  2930. compatible = "arm,psci-0.2";
  2931. method = "smc";
  2932. psci_version = <0x84000000>;
  2933. cpu_suspend = <0xc4000001>;
  2934. cpu_off = <0x84000002>;
  2935. cpu_on = <0xc4000003>;
  2936. affinity_info = <0xc4000004>;
  2937. migrate = <0xc4000005>;
  2938. migrate_info_type = <0x84000006>;
  2939. migrate_info_up_cpu = <0xc4000007>;
  2940. system_off = <0x84000008>;
  2941. system_reset = <0x84000009>;
  2942. };
  2943. n_brom {
  2944. compatible = "allwinner,n-brom";
  2945. reg = <0x00000000 0x00000000 0x00000000 0x0000c000>;
  2946. };
  2947. s_brom {
  2948. compatible = "allwinner,s-brom";
  2949. reg = <0x00000000 0x00000000 0x00000000 0x00010000>;
  2950. };
  2951. sram_a1 {
  2952. compatible = "allwinner,sram_a1";
  2953. reg = <0x00000000 0x00010000 0x00000000 0x00008000>;
  2954. };
  2955. sram_a2 {
  2956. compatible = "allwinner,sram_a2";
  2957. reg = <0x00000000 0x00040000 0x00000000 0x00014000>;
  2958. };
  2959. prcm {
  2960. compatible = "allwinner,prcm";
  2961. reg = <0x00000000 0x01f01400 0x00000000 0x00000400>;
  2962. };
  2963. cpuscfg {
  2964. compatible = "allwinner,cpuscfg";
  2965. reg = <0x00000000 0x01f01c00 0x00000000 0x00000400>;
  2966. };
  2967. ion {
  2968. compatible = "allwinner,sunxi-ion";
  2969. system_contig {
  2970. type = <0x00000001>;
  2971. };
  2972. cma {
  2973. type = <0x00000004>;
  2974. };
  2975. system {
  2976. type = <0x00000000>;
  2977. };
  2978. };
  2979. dram {
  2980. compatible = "allwinner,dram";
  2981. clocks = <0x00000093 0x00000094>;
  2982. clock-names = "pll_ddr0", "pll_ddr1";
  2983. dram_clk = <0x000002a0>;
  2984. dram_type = <0x00000003>;
  2985. dram_zq = <0x003b3bdd>;
  2986. dram_odt_en = <0x00000001>;
  2987. dram_para1 = <0x10e40400>;
  2988. dram_para2 = <0x04000000>;
  2989. dram_mr0 = <0x00001c70>;
  2990. dram_mr1 = <0x00000040>;
  2991. dram_mr2 = <0x00000018>;
  2992. dram_mr3 = <0x00000000>;
  2993. dram_tpr0 = <0x0048a192>;
  2994. dram_tpr1 = <0x01c2418d>;
  2995. dram_tpr2 = <0x00076051>;
  2996. dram_tpr3 = <0x050005dc>;
  2997. dram_tpr4 = <0x00000000>;
  2998. dram_tpr5 = <0x00000000>;
  2999. dram_tpr6 = <0x00000000>;
  3000. dram_tpr7 = <0x2a066198>;
  3001. dram_tpr8 = <0x00000000>;
  3002. dram_tpr9 = <0x00000000>;
  3003. dram_tpr10 = <0x00008808>;
  3004. dram_tpr11 = <0x40a60066>;
  3005. dram_tpr12 = <0x55550000>;
  3006. dram_tpr13 = <0x04000903>;
  3007. device_type = "dram";
  3008. };
  3009. memory@40000000 {
  3010. device_type = "memory";
  3011. reg = <0x00000000 0x41000000 0x00000000 0x3f000000>;
  3012. };
  3013. interrupt-controller@1c81000 {
  3014. compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  3015. #interrupt-cells = <0x00000003>;
  3016. #address-cells = <0x00000000>;
  3017. device_type = "gic";
  3018. interrupt-controller;
  3019. reg = <0x00000000 0x01c81000 0x00000000 0x00001000 0x00000000 0x01c82000 0x00000000 0x00002000 0x00000000 0x01c84000 0x00000000 0x00002000 0x00000000 0x01c86000 0x00000000 0x00002000>;
  3020. interrupts = <0x00000001 0x00000009 0x00000f04>;
  3021. linux,phandle = <0x00000001>;
  3022. phandle = <0x00000001>;
  3023. };
  3024. sunxi-chipid@1c14200 {
  3025. compatible = "sunxi,sun50i-chipid";
  3026. device_type = "chipid";
  3027. reg = <0x00000000 0x01c14200 0x00000000 0x00000400>;
  3028. };
  3029. timer {
  3030. compatible = "arm,armv8-timer";
  3031. interrupts = <0x00000001 0x0000000d 0x0000ff01 0x00000001 0x0000000e 0x0000ff01 0x00000001 0x0000000b 0x0000ff01 0x00000001 0x0000000a 0x0000ff01>;
  3032. clock-frequency = <0x016e3600>;
  3033. };
  3034. pmu {
  3035. compatible = "arm,armv8-pmuv3";
  3036. interrupts = <0x00000000 0x00000078 0x00000004 0x00000000 0x00000079 0x00000004 0x00000000 0x0000007a 0x00000004 0x00000000 0x0000007b 0x00000004>;
  3037. };
  3038. dvfs_table {
  3039. compatible = "allwinner,dvfs_table";
  3040. extremity_freq = <1296000000>;
  3041. max_freq = <1200000000>;
  3042. min_freq = <480000000>;
  3043. lv_count = <7>;
  3044. lv1_freq = <1296000000>;
  3045. lv1_volt = <1280>;
  3046. lv2_freq = <1200000000>;
  3047. lv2_volt = <1240>;
  3048. lv3_freq = <1104000000>;
  3049. lv3_volt = <1180>;
  3050. lv4_freq = <1008000000>;
  3051. lv4_volt = <1120>;
  3052. lv5_freq = <912000000>;
  3053. lv5_volt = <1060>;
  3054. lv6_freq = <816000000>;
  3055. lv6_volt = <1020>;
  3056. lv7_freq = <648000000>;
  3057. lv7_volt = <980>;
  3058. device_type = "dvfs_table";
  3059. };
  3060. dramfreq {
  3061. compatible = "allwinner,sunxi-dramfreq";
  3062. reg = <0x00000000 0x01c62000 0x00000000 0x00001000 0x00000000 0x01c63000 0x00000000 0x00001000 0x00000000 0x01c20000 0x00000000 0x00000800>;
  3063. clocks = <0x00000093 0x00000094 0x00000095>;
  3064. status = "okay";
  3065. };
  3066. uboot {
  3067. };
  3068. gpu@0x01c40000 {
  3069. compatible = "arm,mali-400", "arm,mali-utgard";
  3070. reg = <0x00000000 0x01c40000 0x00000000 0x00010000>;
  3071. interrupts = <0x00000000 0x00000061 0x00000004 0x00000000 0x00000062 0x00000004 0x00000000 0x00000063 0x00000004 0x00000000 0x00000064 0x00000004 0x00000000 0x00000066 0x00000004 0x00000000 0x00000067 0x00000004>;
  3072. interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
  3073. clocks = <0x00000096 0x00000097>;
  3074. device_type = "gpu_mali400_0";
  3075. normal_freq = <0x00000198>;
  3076. scene_ctrl_status = <0x00000000>;
  3077. temp_ctrl_status = <0x00000001>;
  3078. };
  3079. wlan {
  3080. compatible = "allwinner,sunxi-wlan";
  3081. wlan_io_regulator = "vcc-wifi-io";
  3082. wlan_busnum = <0x00000001>;
  3083. status = "okay";
  3084. device_type = "wlan";
  3085. clocks;
  3086. wlan_power;
  3087. wlan_regon = <0x00000079 0x0000000b 0x00000002 0x00000001 0xffffffff 0xffffffff 0x00000000>;
  3088. wlan_hostwake = <0x00000079 0x0000000b 0x00000003 0x00000006 0xffffffff 0xffffffff 0x00000000>;
  3089. efuse_map_path = "wifi_efuse_8189e_for_MB1019Q5.map";
  3090. };
  3091. bt {
  3092. compatible = "allwinner,sunxi-bt";
  3093. bt_io_regulator = "vcc-wifi-io";
  3094. status = "okay";
  3095. device_type = "bt";
  3096. clocks;
  3097. bt_power;
  3098. bt_rst_n = <0x00000079 0x0000000b 0x00000004 0x00000001 0xffffffff 0xffffffff 0x00000000>;
  3099. };
  3100. btlpm {
  3101. compatible = "allwinner,sunxi-btlpm";
  3102. uart_index = <0x00000001>;
  3103. status = "okay";
  3104. device_type = "btlpm";
  3105. bt_wake = <0x00000079 0x0000000b 0x00000006 0x00000001 0xffffffff 0xffffffff 0x00000001>;
  3106. bt_hostwake = <0x00000079 0x0000000b 0x00000005 0x00000006 0xffffffff 0xffffffff 0x00000000>;
  3107. };
  3108. };
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