/* Configure Oscillator to operate the device at 4Mhz */
// Fosc= Fin*M/(N1*N2), Fcy=Fosc/2
// M is PLLDIV + 2
PLLFBDbits.PLLDIV = 41;
// N1 is PLLPRE + 2
CLKDIVbits.PLLPRE = 78;  //N1 is 80
// N2 is 2*(PLLPOST + 1) // N2 is 1
CLKDIVbits.PLLPOST = 0;
// Fosc = Fin * 43/(80) = Fin * 128; 7.37 * 43/ 80 = 4Mhz
// Fcy = Fosc / frcdiv (if 0 then 1)
CLKDIVbits.FRCDIV = 0;

_FOSCSEL(FNOSC_FRCPLL);
CLKDIVBITS.FRCDIV = 0;      //FRC Divid-by-1
OSCTUNbits = 0;     //7.373Mhz

/* Configure Oscillator to operate the device at 4Mhz */
// Fosc= Fin*M/(N1*N2), Fcy=Fosc/2
// M is PLLDIV + 2
PLLFBDbits.PLLDIV = 41;
// N1 is PLLPRE + 2
CLKDIVbits.PLLPRE = 78;  //N1 is 80
// N2 is 2*(PLLPOST + 1) // N2 is 1
CLKDIVbits.PLLPOST = 0;
// Fosc = Fin * 43/(80) = Fin * 128; 7.37 * 43/ 80 = 4Mhz
// Fcy = Fosc / frcdiv (if 0 then 1)
CLKDIVbits.FRCDIV = 0;

// FOSC
#pragma config POSCMD = NONE            // Primary Oscillator Mode Select bits (Primary Oscillator disabled)
#pragma config OSCIOFNC = OFF           // OSC2 Pin Function bit (OSC2 is clock output)
#pragma config IOL1WAY = ON             // Peripheral pin select configuration (Allow only one reconfiguration)
#pragma config FCKSM = CSDCMD           // Clock Switching Mode bits (Both Clock switching and Fail-safe Clock Monitor are disabled)


// FOSCSEL
#pragma config FNOSC = FRCDIVN          // Oscillator Source Selection (Internal Fast RC (FRC) Oscillator with postscaler)
#pragma config PWMLOCK = ON             // PWM Lock Enable bit (Certain PWM registers may only be written after key sequence)
#pragma config IESO = ON                // Two-speed Oscillator Start-up Enable bit (Start up device with FRC, then switch to user-selected oscillator source)