entity Decoder is
    Port ( opCode : in  STD_LOGIC_VECTOR (2 downto 0)
		   selectedOp : out STD_LOGIC_VECTOR (7 downto 0));
end Decoder;

architecture Behavioral of Decoder is
-- signals
signal temp : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
begin
	process(opCode)
	begin
        case opCode is
			when "000" => temp <= "00000001";
			when "001" => temp <= "00000010";
			when "010" => temp <= "00000100";
			when "011" => temp <= "00001000";
			when "100" => temp <= "00010000";
			when "101" => temp <= "00100000";
			when "110" => temp <= "01000000";
			when "111" => temp <= "10000000";
		end case;
	selectedOp <= temp;
	end process;
end Behavioral;