FahrradSchaltung-Original

/*
 * ======== Standard MSP430 includes ========
 */
#include <msp430.h>

/*
 * ======== Grace related includes ========
 */
#include <ti/mcu/msp430/csl/CSL.h>

long int i;
#define FDdelay     for(i=0; i<10000;i++){}
#define RDdelay     for(i=0; i<6000;i++){}

// FD position definitions
#define FDlarge     870 // largest
#define FDmedium    1050 // medium
#define FDsmall     1600 // smallest
#define FDoffset    70
#define FDtrim      13

// large gear = 3
// medium gear = 2
// small gear = 1
int volatile FDstate = 0;

// RD position definitions
#define RD1         2060
#define RD2         1950
#define RD3         1870
#define RD4         1800
#define RD5         1700
#define RD6         1650
#define RD7         1550
#define RDoffset    20

// RDstate
// largest = 7
// smallest = 1
int volatile RDstate = 0;

int main(int argc, char *argv[])
{
     CSL_init();                     // Activate Grace-generated configuration

    // Enter LPM with global interrupt enabled
    __bis_SR_register(LPM0_bits + GIE);

    return (0);
}

void downshift(void)
{
    if (P1IFG & BIT4){
        // front
        // clear the flag
        P1IFG &= ~BIT4;

        if (FDstate == 1){
            // small gear, don't shift
            TA0CCR1 = FDsmall;
            FDstate = 1;
        }else if (FDstate == 2){
            // medium to small
            TA0CCR1 = FDsmall + FDoffset + 30;
            FDdelay;
            TA0CCR1 = FDsmall;
            FDstate = 1;
        }else{
            TA0CCR1 = FDmedium + FDoffset;
            FDdelay;
            TA0CCR1 = FDmedium;
            FDstate = 2;
        }
        FDdelay;
    }else{
        // rear
        // clear the flag
        P1IFG &= ~BIT7;

        switch (RDstate){
            case 7:
                TA1CCR2 = RD6 + 5*RDoffset;
                RDdelay;
                TA1CCR2 = RD6;
                RDstate = 6;
                break;
            case 6:
                TA1CCR2 = RD5 + 5*RDoffset;
                RDdelay;
                TA1CCR2 = RD5;
                RDstate = 5;
                break;
            case 5:
                TA1CCR2 = RD4 + 5*RDoffset;
                RDdelay;
                TA1CCR2 = RD4;
                RDstate = 4;
                break;
            case 4:
                TA1CCR2 = RD3 + 5*RDoffset;
                RDdelay;
                TA1CCR2 = RD3;
                RDstate = 3;
                break;
            case 3:
                TA1CCR2 = RD2 + RDoffset;
                RDdelay;
                TA1CCR2 = RD2;
                RDstate = 2;
                break;
            case 2:
                TA1CCR2 = RD1 + RDoffset;
                RDdelay;
                TA1CCR2 = RD1;
                RDstate = 1;
                break;
            case 1:
                TA1CCR2 = RD1;
                RDstate = 1;
                break;
            default:
                TA1CCR2 = RD1;
                RDstate = 1;
                break;
        }

        FDdelay;

    }
}

void upshift(void)
{
    if (P2IFG & BIT0){
        // front
        // clear the flag
        P2IFG &= ~BIT0;

        if (FDstate == 1){
            // small --> medium
            TA0CCR1 = FDmedium - FDoffset;
            FDdelay;
            TA0CCR1 = FDmedium;
            FDstate = 2;
        }else if (FDstate == 2){
            // medium to large
            TA0CCR1 = FDlarge - FDoffset;
            FDdelay;
            TA0CCR1 = FDlarge;
            FDstate = 3;
        }else{
            //TA0CCR1 = FDlarge;
            //FDstate = 3;
        }

        FDdelay;

    }else{
        // rear
        // clear the flag
        P2IFG &= ~BIT4;

        switch (RDstate){
            case 1:
                TA1CCR2 = RD2 - 5*RDoffset;
                RDdelay;
                TA1CCR2 = RD2;
                RDstate = 2;
                break;
            case 2:
                TA1CCR2 = RD3 - RDoffset;
                RDdelay;
                TA1CCR2 = RD3;
                RDstate = 3;
                break;
            case 3:
                TA1CCR2 = RD4 - RDoffset;
                RDdelay;
                TA1CCR2 = RD4;
                RDstate = 4;
                break;
            case 4:
                TA1CCR2 = RD5 - 0.5*RDoffset;
                RDdelay;
                TA1CCR2 = RD5;
                RDstate = 5;
                break;
            case 5:
                TA1CCR2 = RD6 - RDoffset;
                RDdelay;
                TA1CCR2 = RD6;
                RDstate = 6;
                break;
            case 6:
                TA1CCR2 = RD7 - RDoffset;
                RDdelay;
                TA1CCR2 = RD7;
                RDstate = 7;
                break;
            case 7:
                TA1CCR2 = RD7;
                RDstate = 7;
                break;
            default:
                TA1CCR2 = RD7;
                RDstate = 7;
                break;
        }

        FDdelay;

    }
}

void autotrim(void){
    if (FDstate == 3 && RDstate >= 3){
        TA0CCR1 = FDlarge + FDtrim*(RDstate - 2);
    }else if(FDstate == 3 && RDstate < 3){
        TA0CCR1 = FDlarge;
    }
}