library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity moore is
port(
	Entrada, CLK, RST: IN BIT;
	F: OUT BIT
);
end moore;

architecture fsm of moore is
	subtype state_type is std_logic_vector (2 downto 0);
	signal state: state_type;
	constant A: state_type:="000";
	constant B: state_type:="001";
	constant C: state_type:="011";
	constant D: state_type:="010";
	constant E: state_type:="110";
	signal current_state, next_state: state_type;

begin
	ff: process (CLK, RST)
	begin
	if(RST='1') then
		current_state <= A;
	elsif (CLK'EVENT and CLK='1') then
		current_state <= next_state;
	end if;
end process ff;

logic: process(Entrada, current_state)
	begin
	case current_state is
	when A =>
		if(Entrada='0') then
			next_state <= A;
		else
			next_state <= B;
		end if;
	when B =>
		if(Entrada='0') then
			next_state <= B;
		else
			next_state <= C;
		end if;
	when C =>
		if(Entrada='0') then
			next_state <= D;
		else
			next_state <= C;
		end if;
	when D =>
		if(Entrada='0') then
			next_state <= E;
		else
			next_state <= C;
		end if;
	when E =>
		if(Entrada='0') then
			next_state <= B;
		else
			next_state <= C;
		end if;
	when others =>
		next_state <= A;
	end case;
end process;
F <= '1' when current_state = E else '0';
end fsm;