imx6_gpio.h

volatile uint32_t *gpio;

typedef struct {
    volatile uint32_t *reg_addr;
    char pin_num;
    char claimed;
} imx_gpio_pin;

imx_gpio_pin x21_pins[8] = {
    { (uint32_t *)0x20a8000, 19, 0 }, // pin 0, di0_pin3, 4 reg
    { (uint32_t *)0x209c000,  6, 0 }, // pin 1, gpio_9, 1 reg
    { (uint32_t *)0x209c000,  9, 0 }, // pin 2, gpio_18
    { (uint32_t *)0x20b4000, 12, 0 }, // pin 3, gpio_6, 7 reg
    { (uint32_t *)0x20b4000, 13, 0 }, // pin 4, gpio_17
    { (uint32_t *)0x20a8000,  5, 0 }, // pin 5, gpio_19
    { (uint32_t *)0x20a0000, 23, 0 }, // pin 6, eim_cs0, 2 reg
    { (uint32_t *)0x20a0000, 24, 0 }, // pin 7, eim_cs1
};

imx_gpio_pin x54_pins[11] = {
    { (uint32_t *)0x20ac000,  8, 0 }, // pin 0, 5 reg
    { (uint32_t *)0x20ac000,  7, 0 }, // pin 1
    { (uint32_t *)0x20a8000, 18, 0 }, // pin 2, 4 reg
    { (uint32_t *)0x20a8000, 19, 0 }, // pin 3
    { (uint32_t *)0x209c000,  6, 0 }, // pin 4, 1 reg
    { (uint32_t *)0x209c000,  9, 0 }, // pin 5
    { (uint32_t *)0x20b4000, 12, 0 }, // pin 6, 7 reg
    { (uint32_t *)0x20b4000, 13, 0 }, // pin 7
    { (uint32_t *)0x20a8000,  5, 0 }, // pin 8, 4 reg
    { (uint32_t *)0x20a0000, 23, 0 }, // pin 9, 2 reg
    { (uint32_t *)0x20a0000, 24, 0 }, // pin 10
};