`timescale 1 ns / 1 ns

module CORDIC_ABS
  #(
    parameter INPUT_WIDTH = 16,
    parameter OUTPUT_WIDTH = 16
  )
  (
    input wire clk,
    input wire start,
    input wire signed [INPUT_WIDTH - 1:0] X,
    input wire signed [INPUT_WIDTH - 1:0] Y,
    output reg [OUTPUT_WIDTH - 1: 0] abs = 0,
    output wire ce_out
  );

  localparam WIDTH_XY = OUTPUT_WIDTH;
  localparam iterations = WIDTH_XY;
  localparam STATE_IDLE = 0, STATE_RUN = 1, STATE_STOP = 2;

  reg [1:0] state = STATE_IDLE;

  reg signed [WIDTH_XY - 1:0] x;
  reg signed [WIDTH_XY - 1:0] y;

  reg [$clog2(iterations) - 1:0] iteration_cnt = 0;

  assign ce_out = (state == STATE_STOP);

  always @(posedge clk) begin
    case (state)
      STATE_IDLE: begin
        if (start) begin
          state <= STATE_RUN;
          x <= (X < 0) ? -X : X;
          y <= (Y < 0) ? -Y : Y;
          iteration_cnt <= 0;
        end
      end
      STATE_RUN: begin
        if (y > 0) begin
          x <= x + (y >>> iteration_cnt);
          y <= y - (x >>> iteration_cnt);
        end else begin
          x <= x - (y >>> iteration_cnt);
          y <= y + (x >>> iteration_cnt);
        end
        if (iteration_cnt == iterations - 1) begin
          state <= STATE_STOP;
        end
        iteration_cnt <= iteration_cnt + 1'b1;
      end
      STATE_STOP: begin
        state <= STATE_IDLE;
        abs <= x;
      end
      default: begin
        state <= STATE_IDLE;
      end
    endcase
  end
endmodule