`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:Visnovszky Lilla
//
// Create Date:   13:23:08 10/25/2014
// Design Name:   uart
// Module Name:   C:/.Xilinx/uart/test.v
// Project Name:  uart
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: uart
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module test;

    // Inputs
    reg clk;
    reg rst;
    reg [3:0] bcd0;
    reg [3:0] bcd1;

    // Outputs
    wire tx_out;

    // Instantiate the Unit Under Test (UUT)
    uart uut (
        .clk(clk),
        .rst(rst),
        .bcd0(bcd0),
        .bcd1(bcd1),
        .tx_out(tx_out)
    );

    initial begin
        // Initialize Inputs, alapértékek beállítása
        clk = 0;
        rst = 1;
        bcd0 = 0;
        bcd1 = 0;

        // Wait 100 ns for global reset to finish
        #100;

        // A születési dátumom kivitele: 04.27.
        rst=0;
        bcd0=4;
        bcd1=0;
        #200;
        bcd0=7;
        bcd1=2;

    end
//initial begin
//clk=0;
//rst=1;
//bcd0=4;
//bcd1=0;
//#8;
//rst=0;
//#8
//bcd0=7;
//bcd1=2;
//end

//órajel generálása:
always #1
clk<=~clk;
endmodule