library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity secuencia is
port (clk: in std_logic;
     Q2, Q1, Q0: inout std_logic);
end secuencia;

architecture secuencia_dig of secuencia is
type estados is (d0, d1, d2, d3, d4, d5, d6);
signal e_pst, e_fto: estados;
    begin
    procece1: process (e_pst, Q2, Q1, Q0) begin
        case e_pst is
            when d0 =>  Q2<='0';
                            Q1<='1';
                            Q0<='0';
                            e_fto <= d1;
            when d1=>   Q2<='0';
                            Q1<='0';
                            Q0<='0';
                            e_fto <= d2;
            when d2=>   Q2<='0';
                            Q1<='0';
                            Q0<='1';
                            e_fto <= d3;
            when d3=>   Q2<='0';
                            Q1<='1';
                            Q0<='1';
                            e_fto <= d4;
            when d4=>   Q2<='1';
                            Q1<='1';
                            Q0<='0';
                            e_fto <= d5;
            when d5=>   Q2<='1';
                            Q1<='0';
                            Q0<='0';
                            e_fto <= d6;
            when d6=>   Q2<='1';
                            Q1<='1';
                            Q0<='1';
                            e_fto <= d0;
        end case;
    end process procece1;

    proceso2: process(clk) begin
    if(clk'event and clk ='1') then
    e_pst <= e_fto;
    end if;
    end process;
    end secuencia_dig;