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  1. /*
  2. * Copyright 2013 Maxime Ripard
  3. *
  4. * Maxime Ripard <maxime.ripard@free-electrons.com>
  5. *
  6. * This file is dual-licensed: you can use it either under the terms
  7. * of the GPL or the X11 license, at your option. Note that this dual
  8. * licensing only applies to this file, and not this project as a
  9. * whole.
  10. *
  11. * a) This file is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of the
  14. * License, or (at your option) any later version.
  15. *
  16. * This file is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * Or, alternatively,
  22. *
  23. * b) Permission is hereby granted, free of charge, to any person
  24. * obtaining a copy of this software and associated documentation
  25. * files (the "Software"), to deal in the Software without
  26. * restriction, including without limitation the rights to use,
  27. * copy, modify, merge, publish, distribute, sublicense, and/or
  28. * sell copies of the Software, and to permit persons to whom the
  29. * Software is furnished to do so, subject to the following
  30. * conditions:
  31. *
  32. * The above copyright notice and this permission notice shall be
  33. * included in all copies or substantial portions of the Software.
  34. *
  35. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42. * OTHER DEALINGS IN THE SOFTWARE.
  43. */
  44.  
  45. #include "skeleton.dtsi"
  46.  
  47. #include <dt-bindings/interrupt-controller/arm-gic.h>
  48. #include <dt-bindings/thermal/thermal.h>
  49.  
  50. #include <dt-bindings/clock/sun4i-a10-pll2.h>
  51. #include <dt-bindings/dma/sun4i-a10.h>
  52. #include <dt-bindings/pinctrl/sun4i-a10.h>
  53.  
  54. / {
  55. interrupt-parent = <&gic>;
  56.  
  57. aliases {
  58. ethernet0 = &gmac;
  59. };
  60.  
  61. chosen {
  62. #address-cells = <1>;
  63. #size-cells = <1>;
  64. ranges;
  65.  
  66. framebuffer@0 {
  67. compatible = "allwinner,simple-framebuffer",
  68. "simple-framebuffer";
  69. allwinner,pipeline = "de_be0-lcd0-hdmi";
  70. clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  71. <&ahb_gates 44>;
  72. status = "disabled";
  73. };
  74.  
  75. framebuffer@1 {
  76. compatible = "allwinner,simple-framebuffer",
  77. "simple-framebuffer";
  78. allwinner,pipeline = "de_be0-lcd0";
  79. clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
  80. status = "disabled";
  81. };
  82.  
  83. framebuffer@2 {
  84. compatible = "allwinner,simple-framebuffer",
  85. "simple-framebuffer";
  86. allwinner,pipeline = "de_be0-lcd0-tve0";
  87. clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
  88. <&ahb_gates 44>;
  89. status = "disabled";
  90. };
  91. };
  92.  
  93. cpus {
  94. #address-cells = <1>;
  95. #size-cells = <0>;
  96.  
  97. cpu0: cpu@0 {
  98. compatible = "arm,cortex-a7";
  99. device_type = "cpu";
  100. reg = <0>;
  101. clocks = <&cpu>;
  102. clock-latency = <244144>; /* 8 32k periods */
  103. operating-points = <
  104. /* kHz uV */
  105. 960000 1400000
  106. 912000 1400000
  107. 864000 1300000
  108. 720000 1200000
  109. 528000 1100000
  110. 312000 1000000
  111. 144000 1000000
  112. >;
  113. #cooling-cells = <2>;
  114. cooling-min-level = <0>;
  115. cooling-max-level = <6>;
  116. };
  117.  
  118. cpu@1 {
  119. compatible = "arm,cortex-a7";
  120. device_type = "cpu";
  121. reg = <1>;
  122. };
  123. };
  124.  
  125. thermal-zones {
  126. cpu_thermal {
  127. /* milliseconds */
  128. polling-delay-passive = <250>;
  129. polling-delay = <1000>;
  130. thermal-sensors = <&rtp>;
  131.  
  132. cooling-maps {
  133. map0 {
  134. trip = <&cpu_alert0>;
  135. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  136. };
  137. };
  138.  
  139. trips {
  140. cpu_alert0: cpu_alert0 {
  141. /* milliCelsius */
  142. temperature = <75000>;
  143. hysteresis = <2000>;
  144. type = "passive";
  145. };
  146.  
  147. cpu_crit: cpu_crit {
  148. /* milliCelsius */
  149. temperature = <100000>;
  150. hysteresis = <2000>;
  151. type = "critical";
  152. };
  153. };
  154. };
  155. };
  156.  
  157. memory {
  158. reg = <0x40000000 0x80000000>;
  159. };
  160.  
  161. timer {
  162. compatible = "arm,armv7-timer";
  163. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  164. <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  165. <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  166. <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  167. };
  168.  
  169. pmu {
  170. compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
  171. interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
  172. <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
  173. };
  174.  
  175. clocks {
  176. #address-cells = <1>;
  177. #size-cells = <1>;
  178. ranges;
  179.  
  180. osc24M: clk@01c20050 {
  181. #clock-cells = <0>;
  182. compatible = "allwinner,sun4i-a10-osc-clk";
  183. reg = <0x01c20050 0x4>;
  184. clock-frequency = <24000000>;
  185. clock-output-names = "osc24M";
  186. };
  187.  
  188. osc32k: clk@0 {
  189. #clock-cells = <0>;
  190. compatible = "fixed-clock";
  191. clock-frequency = <32768>;
  192. clock-output-names = "osc32k";
  193. };
  194.  
  195. pll1: clk@01c20000 {
  196. #clock-cells = <0>;
  197. compatible = "allwinner,sun4i-a10-pll1-clk";
  198. reg = <0x01c20000 0x4>;
  199. clocks = <&osc24M>;
  200. clock-output-names = "pll1";
  201. };
  202.  
  203. pll2: clk@01c20008 {
  204. #clock-cells = <1>;
  205. compatible = "allwinner,sun4i-a10-pll2-clk";
  206. reg = <0x01c20008 0x8>;
  207. clocks = <&osc24M>;
  208. clock-output-names = "pll2-1x", "pll2-2x",
  209. "pll2-4x", "pll2-8x";
  210. };
  211.  
  212. pll4: clk@01c20018 {
  213. #clock-cells = <0>;
  214. compatible = "allwinner,sun7i-a20-pll4-clk";
  215. reg = <0x01c20018 0x4>;
  216. clocks = <&osc24M>;
  217. clock-output-names = "pll4";
  218. };
  219.  
  220. pll5: clk@01c20020 {
  221. #clock-cells = <1>;
  222. compatible = "allwinner,sun4i-a10-pll5-clk";
  223. reg = <0x01c20020 0x4>;
  224. clocks = <&osc24M>;
  225. clock-output-names = "pll5_ddr", "pll5_other";
  226. };
  227.  
  228. pll6: clk@01c20028 {
  229. #clock-cells = <1>;
  230. compatible = "allwinner,sun4i-a10-pll6-clk";
  231. reg = <0x01c20028 0x4>;
  232. clocks = <&osc24M>;
  233. clock-output-names = "pll6_sata", "pll6_other", "pll6",
  234. "pll6_div_4";
  235. };
  236.  
  237. pll8: clk@01c20040 {
  238. #clock-cells = <0>;
  239. compatible = "allwinner,sun7i-a20-pll4-clk";
  240. reg = <0x01c20040 0x4>;
  241. clocks = <&osc24M>;
  242. clock-output-names = "pll8";
  243. };
  244.  
  245. cpu: cpu@01c20054 {
  246. #clock-cells = <0>;
  247. compatible = "allwinner,sun4i-a10-cpu-clk";
  248. reg = <0x01c20054 0x4>;
  249. clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
  250. clock-output-names = "cpu";
  251. };
  252.  
  253. axi: axi@01c20054 {
  254. #clock-cells = <0>;
  255. compatible = "allwinner,sun4i-a10-axi-clk";
  256. reg = <0x01c20054 0x4>;
  257. clocks = <&cpu>;
  258. clock-output-names = "axi";
  259. };
  260.  
  261. ahb: ahb@01c20054 {
  262. #clock-cells = <0>;
  263. compatible = "allwinner,sun5i-a13-ahb-clk";
  264. reg = <0x01c20054 0x4>;
  265. clocks = <&axi>, <&pll6 3>, <&pll6 1>;
  266. clock-output-names = "ahb";
  267. /*
  268. * Use PLL6 as parent, instead of CPU/AXI
  269. * which has rate changes due to cpufreq
  270. */
  271. assigned-clocks = <&ahb>;
  272. assigned-clock-parents = <&pll6 3>;
  273. };
  274.  
  275. ahb_gates: clk@01c20060 {
  276. #clock-cells = <1>;
  277. compatible = "allwinner,sun7i-a20-ahb-gates-clk";
  278. reg = <0x01c20060 0x8>;
  279. clocks = <&ahb>;
  280. clock-indices = <0>, <1>,
  281. <2>, <3>, <4>,
  282. <5>, <6>, <7>, <8>,
  283. <9>, <10>, <11>, <12>,
  284. <13>, <14>, <16>,
  285. <17>, <18>, <20>, <21>,
  286. <22>, <23>, <25>,
  287. <28>, <32>, <33>, <34>,
  288. <35>, <36>, <37>, <40>,
  289. <41>, <42>, <43>,
  290. <44>, <45>, <46>,
  291. <47>, <49>, <50>,
  292. <52>;
  293. clock-output-names = "ahb_usb0", "ahb_ehci0",
  294. "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
  295. "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
  296. "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
  297. "ahb_nand", "ahb_sdram", "ahb_ace",
  298. "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
  299. "ahb_spi2", "ahb_spi3", "ahb_sata",
  300. "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
  301. "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
  302. "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
  303. "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
  304. "ahb_de_fe1", "ahb_gmac", "ahb_mp",
  305. "ahb_mali";
  306. };
  307.  
  308. apb0: apb0@01c20054 {
  309. #clock-cells = <0>;
  310. compatible = "allwinner,sun4i-a10-apb0-clk";
  311. reg = <0x01c20054 0x4>;
  312. clocks = <&ahb>;
  313. clock-output-names = "apb0";
  314. };
  315.  
  316. apb0_gates: clk@01c20068 {
  317. #clock-cells = <1>;
  318. compatible = "allwinner,sun7i-a20-apb0-gates-clk";
  319. reg = <0x01c20068 0x4>;
  320. clocks = <&apb0>;
  321. clock-indices = <0>, <1>,
  322. <2>, <3>, <4>,
  323. <5>, <6>, <7>,
  324. <8>, <10>;
  325. clock-output-names = "apb0_codec", "apb0_spdif",
  326. "apb0_ac97", "apb0_iis0", "apb0_iis1",
  327. "apb0_pio", "apb0_ir0", "apb0_ir1",
  328. "apb0_iis2", "apb0_keypad";
  329. };
  330.  
  331. apb1: clk@01c20058 {
  332. #clock-cells = <0>;
  333. compatible = "allwinner,sun4i-a10-apb1-clk";
  334. reg = <0x01c20058 0x4>;
  335. clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
  336. clock-output-names = "apb1";
  337. };
  338.  
  339. apb1_gates: clk@01c2006c {
  340. #clock-cells = <1>;
  341. compatible = "allwinner,sun7i-a20-apb1-gates-clk";
  342. reg = <0x01c2006c 0x4>;
  343. clocks = <&apb1>;
  344. clock-indices = <0>, <1>,
  345. <2>, <3>, <4>,
  346. <5>, <6>, <7>,
  347. <15>, <16>, <17>,
  348. <18>, <19>, <20>,
  349. <21>, <22>, <23>;
  350. clock-output-names = "apb1_i2c0", "apb1_i2c1",
  351. "apb1_i2c2", "apb1_i2c3", "apb1_can",
  352. "apb1_scr", "apb1_ps20", "apb1_ps21",
  353. "apb1_i2c4", "apb1_uart0", "apb1_uart1",
  354. "apb1_uart2", "apb1_uart3", "apb1_uart4",
  355. "apb1_uart5", "apb1_uart6", "apb1_uart7";
  356. };
  357.  
  358. nand_clk: clk@01c20080 {
  359. #clock-cells = <0>;
  360. compatible = "allwinner,sun4i-a10-mod0-clk";
  361. reg = <0x01c20080 0x4>;
  362. clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  363. clock-output-names = "nand";
  364. };
  365.  
  366. ms_clk: clk@01c20084 {
  367. #clock-cells = <0>;
  368. compatible = "allwinner,sun4i-a10-mod0-clk";
  369. reg = <0x01c20084 0x4>;
  370. clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  371. clock-output-names = "ms";
  372. };
  373.  
  374. mmc0_clk: clk@01c20088 {
  375. #clock-cells = <1>;
  376. compatible = "allwinner,sun4i-a10-mmc-clk";
  377. reg = <0x01c20088 0x4>;
  378. clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  379. clock-output-names = "mmc0",
  380. "mmc0_output",
  381. "mmc0_sample";
  382. };
  383.  
  384. mmc1_clk: clk@01c2008c {
  385. #clock-cells = <1>;
  386. compatible = "allwinner,sun4i-a10-mmc-clk";
  387. reg = <0x01c2008c 0x4>;
  388. clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  389. clock-output-names = "mmc1",
  390. "mmc1_output",
  391. "mmc1_sample";
  392. };
  393.  
  394. mmc2_clk: clk@01c20090 {
  395. #clock-cells = <1>;
  396. compatible = "allwinner,sun4i-a10-mmc-clk";
  397. reg = <0x01c20090 0x4>;
  398. clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  399. clock-output-names = "mmc2",
  400. "mmc2_output",
  401. "mmc2_sample";
  402. };
  403.  
  404. mmc3_clk: clk@01c20094 {
  405. #clock-cells = <1>;
  406. compatible = "allwinner,sun4i-a10-mmc-clk";
  407. reg = <0x01c20094 0x4>;
  408. clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  409. clock-output-names = "mmc3",
  410. "mmc3_output",
  411. "mmc3_sample";
  412. };
  413.  
  414. ts_clk: clk@01c20098 {
  415. #clock-cells = <0>;
  416. compatible = "allwinner,sun4i-a10-mod0-clk";
  417. reg = <0x01c20098 0x4>;
  418. clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  419. clock-output-names = "ts";
  420. };
  421.  
  422. ss_clk: clk@01c2009c {
  423. #clock-cells = <0>;
  424. compatible = "allwinner,sun4i-a10-mod0-clk";
  425. reg = <0x01c2009c 0x4>;
  426. clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  427. clock-output-names = "ss";
  428. };
  429.  
  430. spi0_clk: clk@01c200a0 {
  431. #clock-cells = <0>;
  432. compatible = "allwinner,sun4i-a10-mod0-clk";
  433. reg = <0x01c200a0 0x4>;
  434. clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  435. clock-output-names = "spi0";
  436. };
  437.  
  438. spi1_clk: clk@01c200a4 {
  439. #clock-cells = <0>;
  440. compatible = "allwinner,sun4i-a10-mod0-clk";
  441. reg = <0x01c200a4 0x4>;
  442. clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  443. clock-output-names = "spi1";
  444. };
  445.  
  446. spi2_clk: clk@01c200a8 {
  447. #clock-cells = <0>;
  448. compatible = "allwinner,sun4i-a10-mod0-clk";
  449. reg = <0x01c200a8 0x4>;
  450. clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  451. clock-output-names = "spi2";
  452. };
  453.  
  454. pata_clk: clk@01c200ac {
  455. #clock-cells = <0>;
  456. compatible = "allwinner,sun4i-a10-mod0-clk";
  457. reg = <0x01c200ac 0x4>;
  458. clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  459. clock-output-names = "pata";
  460. };
  461.  
  462. ir0_clk: clk@01c200b0 {
  463. #clock-cells = <0>;
  464. compatible = "allwinner,sun4i-a10-mod0-clk";
  465. reg = <0x01c200b0 0x4>;
  466. clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  467. clock-output-names = "ir0";
  468. };
  469.  
  470. ir1_clk: clk@01c200b4 {
  471. #clock-cells = <0>;
  472. compatible = "allwinner,sun4i-a10-mod0-clk";
  473. reg = <0x01c200b4 0x4>;
  474. clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  475. clock-output-names = "ir1";
  476. };
  477.  
  478. keypad_clk: clk@01c200c4 {
  479. #clock-cells = <0>;
  480. compatible = "allwinner,sun4i-a10-mod0-clk";
  481. reg = <0x01c200c4 0x4>;
  482. clocks = <&osc24M>;
  483. clock-output-names = "keypad";
  484. };
  485.  
  486. usb_clk: clk@01c200cc {
  487. #clock-cells = <1>;
  488. #reset-cells = <1>;
  489. compatible = "allwinner,sun4i-a10-usb-clk";
  490. reg = <0x01c200cc 0x4>;
  491. clocks = <&pll6 1>;
  492. clock-output-names = "usb_ohci0", "usb_ohci1",
  493. "usb_phy";
  494. };
  495.  
  496. spi3_clk: clk@01c200d4 {
  497. #clock-cells = <0>;
  498. compatible = "allwinner,sun4i-a10-mod0-clk";
  499. reg = <0x01c200d4 0x4>;
  500. clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  501. clock-output-names = "spi3";
  502. };
  503.  
  504. codec_clk: clk@01c20140 {
  505. #clock-cells = <0>;
  506. compatible = "allwinner,sun4i-a10-codec-clk";
  507. reg = <0x01c20140 0x4>;
  508. clocks = <&pll2 SUN4I_A10_PLL2_1X>;
  509. clock-output-names = "codec";
  510. };
  511.  
  512. mbus_clk: clk@01c2015c {
  513. #clock-cells = <0>;
  514. compatible = "allwinner,sun5i-a13-mbus-clk";
  515. reg = <0x01c2015c 0x4>;
  516. clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
  517. clock-output-names = "mbus";
  518. };
  519.  
  520. /*
  521. * The following two are dummy clocks, placeholders
  522. * used in the gmac_tx clock. The gmac driver will
  523. * choose one parent depending on the PHY interface
  524. * mode, using clk_set_rate auto-reparenting.
  525. *
  526. * The actual TX clock rate is not controlled by the
  527. * gmac_tx clock.
  528. */
  529. mii_phy_tx_clk: clk@2 {
  530. #clock-cells = <0>;
  531. compatible = "fixed-clock";
  532. clock-frequency = <25000000>;
  533. clock-output-names = "mii_phy_tx";
  534. };
  535.  
  536. gmac_int_tx_clk: clk@3 {
  537. #clock-cells = <0>;
  538. compatible = "fixed-clock";
  539. clock-frequency = <125000000>;
  540. clock-output-names = "gmac_int_tx";
  541. };
  542.  
  543. gmac_tx_clk: clk@01c20164 {
  544. #clock-cells = <0>;
  545. compatible = "allwinner,sun7i-a20-gmac-clk";
  546. reg = <0x01c20164 0x4>;
  547. clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
  548. clock-output-names = "gmac_tx";
  549. };
  550.  
  551. /*
  552. * Dummy clock used by output clocks
  553. */
  554. osc24M_32k: clk@1 {
  555. #clock-cells = <0>;
  556. compatible = "fixed-factor-clock";
  557. clock-div = <750>;
  558. clock-mult = <1>;
  559. clocks = <&osc24M>;
  560. clock-output-names = "osc24M_32k";
  561. };
  562.  
  563. clk_out_a: clk@01c201f0 {
  564. #clock-cells = <0>;
  565. compatible = "allwinner,sun7i-a20-out-clk";
  566. reg = <0x01c201f0 0x4>;
  567. clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
  568. clock-output-names = "clk_out_a";
  569. };
  570.  
  571. clk_out_b: clk@01c201f4 {
  572. #clock-cells = <0>;
  573. compatible = "allwinner,sun7i-a20-out-clk";
  574. reg = <0x01c201f4 0x4>;
  575. clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
  576. clock-output-names = "clk_out_b";
  577. };
  578. };
  579.  
  580. soc@01c00000 {
  581. compatible = "simple-bus";
  582. #address-cells = <1>;
  583. #size-cells = <1>;
  584. ranges;
  585.  
  586. sram-controller@01c00000 {
  587. compatible = "allwinner,sun4i-a10-sram-controller";
  588. reg = <0x01c00000 0x30>;
  589. #address-cells = <1>;
  590. #size-cells = <1>;
  591. ranges;
  592.  
  593. sram_a: sram@00000000 {
  594. compatible = "mmio-sram";
  595. reg = <0x00000000 0xc000>;
  596. #address-cells = <1>;
  597. #size-cells = <1>;
  598. ranges = <0 0x00000000 0xc000>;
  599.  
  600. emac_sram: sram-section@8000 {
  601. compatible = "allwinner,sun4i-a10-sram-a3-a4";
  602. reg = <0x8000 0x4000>;
  603. status = "disabled";
  604. };
  605. };
  606.  
  607. sram_d: sram@00010000 {
  608. compatible = "mmio-sram";
  609. reg = <0x00010000 0x1000>;
  610. #address-cells = <1>;
  611. #size-cells = <1>;
  612. ranges = <0 0x00010000 0x1000>;
  613.  
  614. otg_sram: sram-section@0000 {
  615. compatible = "allwinner,sun4i-a10-sram-d";
  616. reg = <0x0000 0x1000>;
  617. status = "disabled";
  618. };
  619. };
  620. };
  621.  
  622. nmi_intc: interrupt-controller@01c00030 {
  623. compatible = "allwinner,sun7i-a20-sc-nmi";
  624. interrupt-controller;
  625. #interrupt-cells = <2>;
  626. reg = <0x01c00030 0x0c>;
  627. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  628. };
  629.  
  630. dma: dma-controller@01c02000 {
  631. compatible = "allwinner,sun4i-a10-dma";
  632. reg = <0x01c02000 0x1000>;
  633. interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
  634. clocks = <&ahb_gates 6>;
  635. #dma-cells = <2>;
  636. };
  637.  
  638. spi0: spi@01c05000 {
  639. compatible = "allwinner,sun4i-a10-spi";
  640. reg = <0x01c05000 0x1000>;
  641. interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  642. clocks = <&ahb_gates 20>, <&spi0_clk>;
  643. clock-names = "ahb", "mod";
  644. dmas = <&dma SUN4I_DMA_DEDICATED 27>,
  645. <&dma SUN4I_DMA_DEDICATED 26>;
  646. dma-names = "rx", "tx";
  647. status = "disabled";
  648. #address-cells = <1>;
  649. #size-cells = <0>;
  650. };
  651.  
  652. spi1: spi@01c06000 {
  653. compatible = "allwinner,sun4i-a10-spi";
  654. reg = <0x01c06000 0x1000>;
  655. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  656. clocks = <&ahb_gates 21>, <&spi1_clk>;
  657. clock-names = "ahb", "mod";
  658. dmas = <&dma SUN4I_DMA_DEDICATED 9>,
  659. <&dma SUN4I_DMA_DEDICATED 8>;
  660. dma-names = "rx", "tx";
  661. status = "disabled";
  662. #address-cells = <1>;
  663. #size-cells = <0>;
  664. };
  665.  
  666. emac: ethernet@01c0b000 {
  667. compatible = "allwinner,sun4i-a10-emac";
  668. reg = <0x01c0b000 0x1000>;
  669. interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
  670. clocks = <&ahb_gates 17>;
  671. allwinner,sram = <&emac_sram 1>;
  672. status = "disabled";
  673. };
  674.  
  675. mdio: mdio@01c0b080 {
  676. compatible = "allwinner,sun4i-a10-mdio";
  677. reg = <0x01c0b080 0x14>;
  678. status = "disabled";
  679. #address-cells = <1>;
  680. #size-cells = <0>;
  681. };
  682.  
  683. mmc0: mmc@01c0f000 {
  684. compatible = "allwinner,sun5i-a13-mmc";
  685. reg = <0x01c0f000 0x1000>;
  686. clocks = <&ahb_gates 8>,
  687. <&mmc0_clk 0>,
  688. <&mmc0_clk 1>,
  689. <&mmc0_clk 2>;
  690. clock-names = "ahb",
  691. "mmc",
  692. "output",
  693. "sample";
  694. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  695. status = "disabled";
  696. #address-cells = <1>;
  697. #size-cells = <0>;
  698. };
  699.  
  700. mmc1: mmc@01c10000 {
  701. compatible = "allwinner,sun5i-a13-mmc";
  702. reg = <0x01c10000 0x1000>;
  703. clocks = <&ahb_gates 9>,
  704. <&mmc1_clk 0>,
  705. <&mmc1_clk 1>,
  706. <&mmc1_clk 2>;
  707. clock-names = "ahb",
  708. "mmc",
  709. "output",
  710. "sample";
  711. interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  712. status = "disabled";
  713. #address-cells = <1>;
  714. #size-cells = <0>;
  715. };
  716.  
  717. mmc2: mmc@01c11000 {
  718. compatible = "allwinner,sun5i-a13-mmc";
  719. reg = <0x01c11000 0x1000>;
  720. clocks = <&ahb_gates 10>,
  721. <&mmc2_clk 0>,
  722. <&mmc2_clk 1>,
  723. <&mmc2_clk 2>;
  724. clock-names = "ahb",
  725. "mmc",
  726. "output",
  727. "sample";
  728. interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  729. status = "disabled";
  730. #address-cells = <1>;
  731. #size-cells = <0>;
  732. };
  733.  
  734. mmc3: mmc@01c12000 {
  735. compatible = "allwinner,sun5i-a13-mmc";
  736. reg = <0x01c12000 0x1000>;
  737. clocks = <&ahb_gates 11>,
  738. <&mmc3_clk 0>,
  739. <&mmc3_clk 1>,
  740. <&mmc3_clk 2>;
  741. clock-names = "ahb",
  742. "mmc",
  743. "output",
  744. "sample";
  745. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  746. status = "disabled";
  747. #address-cells = <1>;
  748. #size-cells = <0>;
  749. };
  750.  
  751. usb_otg: usb@01c13000 {
  752. compatible = "allwinner,sun4i-a10-musb";
  753. reg = <0x01c13000 0x0400>;
  754. clocks = <&ahb_gates 0>;
  755. interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
  756. interrupt-names = "mc";
  757. phys = <&usbphy 0>;
  758. phy-names = "usb";
  759. extcon = <&usbphy 0>;
  760. allwinner,sram = <&otg_sram 1>;
  761. status = "disabled";
  762. };
  763.  
  764. usbphy: phy@01c13400 {
  765. #phy-cells = <1>;
  766. compatible = "allwinner,sun7i-a20-usb-phy";
  767. reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
  768. reg-names = "phy_ctrl", "pmu1", "pmu2";
  769. clocks = <&usb_clk 8>;
  770. clock-names = "usb_phy";
  771. resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
  772. reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
  773. status = "disabled";
  774. };
  775.  
  776. ehci0: usb@01c14000 {
  777. compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
  778. reg = <0x01c14000 0x100>;
  779. interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
  780. clocks = <&ahb_gates 1>;
  781. phys = <&usbphy 1>;
  782. phy-names = "usb";
  783. status = "disabled";
  784. };
  785.  
  786. ohci0: usb@01c14400 {
  787. compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
  788. reg = <0x01c14400 0x100>;
  789. interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
  790. clocks = <&usb_clk 6>, <&ahb_gates 2>;
  791. phys = <&usbphy 1>;
  792. phy-names = "usb";
  793. status = "disabled";
  794. };
  795.  
  796. crypto: crypto-engine@01c15000 {
  797. compatible = "allwinner,sun4i-a10-crypto";
  798. reg = <0x01c15000 0x1000>;
  799. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  800. clocks = <&ahb_gates 5>, <&ss_clk>;
  801. clock-names = "ahb", "mod";
  802. };
  803.  
  804. spi2: spi@01c17000 {
  805. compatible = "allwinner,sun4i-a10-spi";
  806. reg = <0x01c17000 0x1000>;
  807. interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  808. clocks = <&ahb_gates 22>, <&spi2_clk>;
  809. clock-names = "ahb", "mod";
  810. dmas = <&dma SUN4I_DMA_DEDICATED 29>,
  811. <&dma SUN4I_DMA_DEDICATED 28>;
  812. dma-names = "rx", "tx";
  813. status = "disabled";
  814. #address-cells = <1>;
  815. #size-cells = <0>;
  816. };
  817.  
  818. ahci: sata@01c18000 {
  819. compatible = "allwinner,sun4i-a10-ahci";
  820. reg = <0x01c18000 0x1000>;
  821. interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
  822. clocks = <&pll6 0>, <&ahb_gates 25>;
  823. status = "disabled";
  824. };
  825.  
  826. ehci1: usb@01c1c000 {
  827. compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
  828. reg = <0x01c1c000 0x100>;
  829. interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
  830. clocks = <&ahb_gates 3>;
  831. phys = <&usbphy 2>;
  832. phy-names = "usb";
  833. status = "disabled";
  834. };
  835.  
  836. ohci1: usb@01c1c400 {
  837. compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
  838. reg = <0x01c1c400 0x100>;
  839. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  840. clocks = <&usb_clk 7>, <&ahb_gates 4>;
  841. phys = <&usbphy 2>;
  842. phy-names = "usb";
  843. status = "disabled";
  844. };
  845.  
  846. spi3: spi@01c1f000 {
  847. compatible = "allwinner,sun4i-a10-spi";
  848. reg = <0x01c1f000 0x1000>;
  849. interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
  850. clocks = <&ahb_gates 23>, <&spi3_clk>;
  851. clock-names = "ahb", "mod";
  852. dmas = <&dma SUN4I_DMA_DEDICATED 31>,
  853. <&dma SUN4I_DMA_DEDICATED 30>;
  854. dma-names = "rx", "tx";
  855. status = "disabled";
  856. #address-cells = <1>;
  857. #size-cells = <0>;
  858. };
  859.  
  860. pio: pinctrl@01c20800 {
  861. compatible = "allwinner,sun7i-a20-pinctrl";
  862. reg = <0x01c20800 0x400>;
  863. interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  864. clocks = <&apb0_gates 5>;
  865. gpio-controller;
  866. interrupt-controller;
  867. #interrupt-cells = <3>;
  868. #gpio-cells = <3>;
  869.  
  870. pwm0_pins_a: pwm0@0 {
  871. allwinner,pins = "PB2";
  872. allwinner,function = "pwm";
  873. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  874. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  875. };
  876.  
  877. pwm1_pins_a: pwm1@0 {
  878. allwinner,pins = "PI3";
  879. allwinner,function = "pwm";
  880. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  881. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  882. };
  883.  
  884. uart0_pins_a: uart0@0 {
  885. allwinner,pins = "PB22", "PB23";
  886. allwinner,function = "uart0";
  887. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  888. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  889. };
  890.  
  891. uart2_pins_a: uart2@0 {
  892. allwinner,pins = "PI16", "PI17", "PI18", "PI19";
  893. allwinner,function = "uart2";
  894. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  895. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  896. };
  897.  
  898. uart3_pins_a: uart3@0 {
  899. allwinner,pins = "PG6", "PG7", "PG8", "PG9";
  900. allwinner,function = "uart3";
  901. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  902. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  903. };
  904.  
  905. uart3_pins_b: uart3@1 {
  906. allwinner,pins = "PH0", "PH1";
  907. allwinner,function = "uart3";
  908. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  909. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  910. };
  911.  
  912. uart4_pins_a: uart4@0 {
  913. allwinner,pins = "PG10", "PG11";
  914. allwinner,function = "uart4";
  915. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  916. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  917. };
  918.  
  919. uart4_pins_b: uart4@1 {
  920. allwinner,pins = "PH4", "PH5";
  921. allwinner,function = "uart4";
  922. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  923. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  924. };
  925.  
  926. uart5_pins_a: uart5@0 {
  927. allwinner,pins = "PI10", "PI11";
  928. allwinner,function = "uart5";
  929. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  930. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  931. };
  932.  
  933. uart6_pins_a: uart6@0 {
  934. allwinner,pins = "PI12", "PI13";
  935. allwinner,function = "uart6";
  936. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  937. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  938. };
  939.  
  940. uart7_pins_a: uart7@0 {
  941. allwinner,pins = "PI20", "PI21";
  942. allwinner,function = "uart7";
  943. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  944. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  945. };
  946.  
  947. i2c0_pins_a: i2c0@0 {
  948. allwinner,pins = "PB0", "PB1";
  949. allwinner,function = "i2c0";
  950. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  951. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  952. };
  953.  
  954. i2c1_pins_a: i2c1@0 {
  955. allwinner,pins = "PB18", "PB19";
  956. allwinner,function = "i2c1";
  957. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  958. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  959. };
  960.  
  961. i2c2_pins_a: i2c2@0 {
  962. allwinner,pins = "PB20", "PB21";
  963. allwinner,function = "i2c2";
  964. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  965. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  966. };
  967.  
  968. i2c3_pins_a: i2c3@0 {
  969. allwinner,pins = "PI0", "PI1";
  970. allwinner,function = "i2c3";
  971. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  972. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  973. };
  974.  
  975. emac_pins_a: emac0@0 {
  976. allwinner,pins = "PA0", "PA1", "PA2",
  977. "PA3", "PA4", "PA5", "PA6",
  978. "PA7", "PA8", "PA9", "PA10",
  979. "PA11", "PA12", "PA13", "PA14",
  980. "PA15", "PA16";
  981. allwinner,function = "emac";
  982. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  983. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  984. };
  985.  
  986. clk_out_a_pins_a: clk_out_a@0 {
  987. allwinner,pins = "PI12";
  988. allwinner,function = "clk_out_a";
  989. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  990. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  991. };
  992.  
  993. clk_out_b_pins_a: clk_out_b@0 {
  994. allwinner,pins = "PI13";
  995. allwinner,function = "clk_out_b";
  996. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  997. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  998. };
  999.  
  1000. gmac_pins_mii_a: gmac_mii@0 {
  1001. allwinner,pins = "PA0", "PA1", "PA2",
  1002. "PA3", "PA4", "PA5", "PA6",
  1003. "PA7", "PA8", "PA9", "PA10",
  1004. "PA11", "PA12", "PA13", "PA14",
  1005. "PA15", "PA16";
  1006. allwinner,function = "gmac";
  1007. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  1008. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1009. };
  1010.  
  1011. gmac_pins_rgmii_a: gmac_rgmii@0 {
  1012. allwinner,pins = "PA0", "PA1", "PA2",
  1013. "PA3", "PA4", "PA5", "PA6",
  1014. "PA7", "PA8", "PA10",
  1015. "PA11", "PA12", "PA13",
  1016. "PA15", "PA16";
  1017. allwinner,function = "gmac";
  1018. /*
  1019. * data lines in RGMII mode use DDR mode
  1020. * and need a higher signal drive strength
  1021. */
  1022. allwinner,drive = <SUN4I_PINCTRL_40_MA>;
  1023. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1024. };
  1025.  
  1026. spi0_pins_a: spi0@0 {
  1027. allwinner,pins = "PI11", "PI12", "PI13";
  1028. allwinner,function = "spi0";
  1029. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  1030. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1031. };
  1032.  
  1033. spi0_cs0_pins_a: spi0_cs0@0 {
  1034. allwinner,pins = "PI10";
  1035. allwinner,function = "spi0";
  1036. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  1037. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1038. };
  1039.  
  1040. spi0_cs1_pins_a: spi0_cs1@0 {
  1041. allwinner,pins = "PI14";
  1042. allwinner,function = "spi0";
  1043. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  1044. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1045. };
  1046.  
  1047. spi1_pins_a: spi1@0 {
  1048. allwinner,pins = "PI17", "PI18", "PI19";
  1049. allwinner,function = "spi1";
  1050. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  1051. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1052. };
  1053.  
  1054. spi1_cs0_pins_a: spi1_cs0@0 {
  1055. allwinner,pins = "PI16";
  1056. allwinner,function = "spi1";
  1057. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  1058. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1059. };
  1060.  
  1061. spi2_pins_a: spi2@0 {
  1062. allwinner,pins = "PC20", "PC21", "PC22";
  1063. allwinner,function = "spi2";
  1064. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  1065. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1066. };
  1067.  
  1068. spi2_pins_b: spi2@1 {
  1069. allwinner,pins = "PB15", "PB16", "PB17";
  1070. allwinner,function = "spi2";
  1071. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  1072. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1073. };
  1074.  
  1075. spi2_cs0_pins_a: spi2_cs0@0 {
  1076. allwinner,pins = "PC19";
  1077. allwinner,function = "spi2";
  1078. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  1079. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1080. };
  1081.  
  1082. spi2_cs0_pins_b: spi2_cs0@1 {
  1083. allwinner,pins = "PB14";
  1084. allwinner,function = "spi2";
  1085. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  1086. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1087. };
  1088.  
  1089. mmc0_pins_a: mmc0@0 {
  1090. allwinner,pins = "PF0", "PF1", "PF2",
  1091. "PF3", "PF4", "PF5";
  1092. allwinner,function = "mmc0";
  1093. allwinner,drive = <SUN4I_PINCTRL_30_MA>;
  1094. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1095. };
  1096.  
  1097. mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
  1098. allwinner,pins = "PH1";
  1099. allwinner,function = "gpio_in";
  1100. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  1101. allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  1102. };
  1103.  
  1104. mmc2_pins_a: mmc2@0 {
  1105. allwinner,pins = "PC6", "PC7", "PC8",
  1106. "PC9", "PC10", "PC11";
  1107. allwinner,function = "mmc2";
  1108. allwinner,drive = <SUN4I_PINCTRL_30_MA>;
  1109. allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  1110. };
  1111.  
  1112. mmc3_pins_a: mmc3@0 {
  1113. allwinner,pins = "PI4", "PI5", "PI6",
  1114. "PI7", "PI8", "PI9";
  1115. allwinner,function = "mmc3";
  1116. allwinner,drive = <SUN4I_PINCTRL_30_MA>;
  1117. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1118. };
  1119.  
  1120. ir0_rx_pins_a: ir0@0 {
  1121. allwinner,pins = "PB4";
  1122. allwinner,function = "ir0";
  1123. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  1124. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1125. };
  1126.  
  1127. ir0_tx_pins_a: ir0@1 {
  1128. allwinner,pins = "PB3";
  1129. allwinner,function = "ir0";
  1130. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  1131. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1132. };
  1133.  
  1134. ir1_rx_pins_a: ir1@0 {
  1135. allwinner,pins = "PB23";
  1136. allwinner,function = "ir1";
  1137. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  1138. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1139. };
  1140.  
  1141. ir1_tx_pins_a: ir1@1 {
  1142. allwinner,pins = "PB22";
  1143. allwinner,function = "ir1";
  1144. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  1145. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1146. };
  1147.  
  1148. ps20_pins_a: ps20@0 {
  1149. allwinner,pins = "PI20", "PI21";
  1150. allwinner,function = "ps2";
  1151. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  1152. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1153. };
  1154.  
  1155. ps21_pins_a: ps21@0 {
  1156. allwinner,pins = "PH12", "PH13";
  1157. allwinner,function = "ps2";
  1158. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  1159. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1160. };
  1161. };
  1162.  
  1163. timer@01c20c00 {
  1164. compatible = "allwinner,sun4i-a10-timer";
  1165. reg = <0x01c20c00 0x90>;
  1166. interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
  1167. <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
  1168. <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
  1169. <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
  1170. <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
  1171. <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
  1172. clocks = <&osc24M>;
  1173. };
  1174.  
  1175. wdt: watchdog@01c20c90 {
  1176. compatible = "allwinner,sun4i-a10-wdt";
  1177. reg = <0x01c20c90 0x10>;
  1178. };
  1179.  
  1180. rtc: rtc@01c20d00 {
  1181. compatible = "allwinner,sun7i-a20-rtc";
  1182. reg = <0x01c20d00 0x20>;
  1183. interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
  1184. };
  1185.  
  1186. pwm: pwm@01c20e00 {
  1187. compatible = "allwinner,sun7i-a20-pwm";
  1188. reg = <0x01c20e00 0xc>;
  1189. clocks = <&osc24M>;
  1190. #pwm-cells = <3>;
  1191. status = "disabled";
  1192. };
  1193.  
  1194. ir0: ir@01c21800 {
  1195. compatible = "allwinner,sun4i-a10-ir";
  1196. clocks = <&apb0_gates 6>, <&ir0_clk>;
  1197. clock-names = "apb", "ir";
  1198. interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  1199. reg = <0x01c21800 0x40>;
  1200. status = "disabled";
  1201. };
  1202.  
  1203. ir1: ir@01c21c00 {
  1204. compatible = "allwinner,sun4i-a10-ir";
  1205. clocks = <&apb0_gates 7>, <&ir1_clk>;
  1206. clock-names = "apb", "ir";
  1207. interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  1208. reg = <0x01c21c00 0x40>;
  1209. status = "disabled";
  1210. };
  1211.  
  1212. lradc: lradc@01c22800 {
  1213. compatible = "allwinner,sun4i-a10-lradc-keys";
  1214. reg = <0x01c22800 0x100>;
  1215. interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  1216. status = "disabled";
  1217. };
  1218.  
  1219. codec: codec@01c22c00 {
  1220. #sound-dai-cells = <0>;
  1221. compatible = "allwinner,sun7i-a20-codec";
  1222. reg = <0x01c22c00 0x40>;
  1223. interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  1224. clocks = <&apb0_gates 0>, <&codec_clk>;
  1225. clock-names = "apb", "codec";
  1226. dmas = <&dma SUN4I_DMA_NORMAL 19>,
  1227. <&dma SUN4I_DMA_NORMAL 19>;
  1228. dma-names = "rx", "tx";
  1229. status = "disabled";
  1230. };
  1231.  
  1232. sid: eeprom@01c23800 {
  1233. compatible = "allwinner,sun7i-a20-sid";
  1234. reg = <0x01c23800 0x200>;
  1235. };
  1236.  
  1237. rtp: rtp@01c25000 {
  1238. compatible = "allwinner,sun5i-a13-ts";
  1239. reg = <0x01c25000 0x100>;
  1240. interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  1241. #thermal-sensor-cells = <0>;
  1242. };
  1243.  
  1244. uart0: serial@01c28000 {
  1245. compatible = "snps,dw-apb-uart";
  1246. reg = <0x01c28000 0x400>;
  1247. interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  1248. reg-shift = <2>;
  1249. reg-io-width = <4>;
  1250. clocks = <&apb1_gates 16>;
  1251. status = "disabled";
  1252. };
  1253.  
  1254. uart1: serial@01c28400 {
  1255. compatible = "snps,dw-apb-uart";
  1256. reg = <0x01c28400 0x400>;
  1257. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  1258. reg-shift = <2>;
  1259. reg-io-width = <4>;
  1260. clocks = <&apb1_gates 17>;
  1261. status = "disabled";
  1262. };
  1263.  
  1264. uart2: serial@01c28800 {
  1265. compatible = "snps,dw-apb-uart";
  1266. reg = <0x01c28800 0x400>;
  1267. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  1268. reg-shift = <2>;
  1269. reg-io-width = <4>;
  1270. clocks = <&apb1_gates 18>;
  1271. status = "disabled";
  1272. };
  1273.  
  1274. uart3: serial@01c28c00 {
  1275. compatible = "snps,dw-apb-uart";
  1276. reg = <0x01c28c00 0x400>;
  1277. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  1278. reg-shift = <2>;
  1279. reg-io-width = <4>;
  1280. clocks = <&apb1_gates 19>;
  1281. status = "disabled";
  1282. };
  1283.  
  1284. uart4: serial@01c29000 {
  1285. compatible = "snps,dw-apb-uart";
  1286. reg = <0x01c29000 0x400>;
  1287. interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  1288. reg-shift = <2>;
  1289. reg-io-width = <4>;
  1290. clocks = <&apb1_gates 20>;
  1291. status = "disabled";
  1292. };
  1293.  
  1294. uart5: serial@01c29400 {
  1295. compatible = "snps,dw-apb-uart";
  1296. reg = <0x01c29400 0x400>;
  1297. interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
  1298. reg-shift = <2>;
  1299. reg-io-width = <4>;
  1300. clocks = <&apb1_gates 21>;
  1301. status = "disabled";
  1302. };
  1303.  
  1304. uart6: serial@01c29800 {
  1305. compatible = "snps,dw-apb-uart";
  1306. reg = <0x01c29800 0x400>;
  1307. interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  1308. reg-shift = <2>;
  1309. reg-io-width = <4>;
  1310. clocks = <&apb1_gates 22>;
  1311. status = "disabled";
  1312. };
  1313.  
  1314. uart7: serial@01c29c00 {
  1315. compatible = "snps,dw-apb-uart";
  1316. reg = <0x01c29c00 0x400>;
  1317. interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  1318. reg-shift = <2>;
  1319. reg-io-width = <4>;
  1320. clocks = <&apb1_gates 23>;
  1321. status = "disabled";
  1322. };
  1323.  
  1324. i2c0: i2c@01c2ac00 {
  1325. compatible = "allwinner,sun7i-a20-i2c",
  1326. "allwinner,sun4i-a10-i2c";
  1327. reg = <0x01c2ac00 0x400>;
  1328. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  1329. clocks = <&apb1_gates 0>;
  1330. status = "disabled";
  1331. #address-cells = <1>;
  1332. #size-cells = <0>;
  1333. };
  1334.  
  1335. i2c1: i2c@01c2b000 {
  1336. compatible = "allwinner,sun7i-a20-i2c",
  1337. "allwinner,sun4i-a10-i2c";
  1338. reg = <0x01c2b000 0x400>;
  1339. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  1340. clocks = <&apb1_gates 1>;
  1341. status = "disabled";
  1342. #address-cells = <1>;
  1343. #size-cells = <0>;
  1344. };
  1345.  
  1346. i2c2: i2c@01c2b400 {
  1347. compatible = "allwinner,sun7i-a20-i2c",
  1348. "allwinner,sun4i-a10-i2c";
  1349. reg = <0x01c2b400 0x400>;
  1350. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  1351. clocks = <&apb1_gates 2>;
  1352. status = "disabled";
  1353. #address-cells = <1>;
  1354. #size-cells = <0>;
  1355. };
  1356.  
  1357. i2c3: i2c@01c2b800 {
  1358. compatible = "allwinner,sun7i-a20-i2c",
  1359. "allwinner,sun4i-a10-i2c";
  1360. reg = <0x01c2b800 0x400>;
  1361. interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
  1362. clocks = <&apb1_gates 3>;
  1363. status = "disabled";
  1364. #address-cells = <1>;
  1365. #size-cells = <0>;
  1366. };
  1367.  
  1368. i2c4: i2c@01c2c000 {
  1369. compatible = "allwinner,sun7i-a20-i2c",
  1370. "allwinner,sun4i-a10-i2c";
  1371. reg = <0x01c2c000 0x400>;
  1372. interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
  1373. clocks = <&apb1_gates 15>;
  1374. status = "disabled";
  1375. #address-cells = <1>;
  1376. #size-cells = <0>;
  1377. };
  1378.  
  1379. gmac: ethernet@01c50000 {
  1380. compatible = "allwinner,sun7i-a20-gmac";
  1381. reg = <0x01c50000 0x10000>;
  1382. interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  1383. interrupt-names = "macirq";
  1384. clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
  1385. clock-names = "stmmaceth", "allwinner_gmac_tx";
  1386. snps,pbl = <2>;
  1387. snps,fixed-burst;
  1388. snps,force_sf_dma_mode;
  1389. status = "disabled";
  1390. #address-cells = <1>;
  1391. #size-cells = <0>;
  1392. };
  1393.  
  1394. hstimer@01c60000 {
  1395. compatible = "allwinner,sun7i-a20-hstimer";
  1396. reg = <0x01c60000 0x1000>;
  1397. interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
  1398. <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
  1399. <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
  1400. <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
  1401. clocks = <&ahb_gates 28>;
  1402. };
  1403.  
  1404. gic: interrupt-controller@01c81000 {
  1405. compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
  1406. reg = <0x01c81000 0x1000>,
  1407. <0x01c82000 0x1000>,
  1408. <0x01c84000 0x2000>,
  1409. <0x01c86000 0x2000>;
  1410. interrupt-controller;
  1411. #interrupt-cells = <3>;
  1412. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  1413. };
  1414.  
  1415. ps20: ps2@01c2a000 {
  1416. compatible = "allwinner,sun4i-a10-ps2";
  1417. reg = <0x01c2a000 0x400>;
  1418. interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
  1419. clocks = <&apb1_gates 6>;
  1420. status = "disabled";
  1421. };
  1422.  
  1423. ps21: ps2@01c2a400 {
  1424. compatible = "allwinner,sun4i-a10-ps2";
  1425. reg = <0x01c2a400 0x400>;
  1426. interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  1427. clocks = <&apb1_gates 7>;
  1428. status = "disabled";
  1429. };
  1430. };
  1431. };
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