module TwoPButterfly( input wire en, input wire clk, input wire [63:0]inr1,ini1,inr2,ini2,
								output reg [63:0]outr1,outi1,outr2,outi2);

add_sub adder1(en,clk,inr1[63],inr2[63],inr1[62:52],inr2[62:52],inr1[51:0],inr2[51:0],1'b0,outr1[63],outr1[62:52],outr1[51:0]);
add_sub adder2(en,clk,ini1[63],ini2[63],ini1[62:52],ini2[62:52],ini1[51:0],ini2[51:0],1'b0,outi1[63],outi1[62:52],outi1[51:0]);


add_sub subtractor1(en,clk,inr1[63],inr2[63],inr1[62:52],inr2[62:52],inr1[51:0],inr2[51:0],1'b1,outr2[63],outr2[62:52],outr2[51:0]);
add_sub subtractor2(en,clk,ini1[63],ini2[63],ini1[62:52],ini2[62:52],ini1[51:0],ini2[51:0],1'b1,outi2[63],outi2[62:52],outi2[51:0]);

endmodule

---------------------------------------------------------------
// adder/subtractor module
module add_sub(input wire en, input wire clk, input wire S1,S2,
			   input wire[10:0]E1, input wire [10:0]E2,
			   input wire[51:0]F1,input wire [51:0]F2,
					input wire aors,
							 output reg S,output reg[10:0]E,output reg[51:0]F);

wire [63:0]in1,in2,out;
reg [10:0]e,Ei;
wire [52:0]f1,f2;
reg [52:0]f,Fs,Fi1;
reg [53:0]Fi;
wire s1,s2;
assign f1={1'b1,F1};
assign f2={1'b1,F2};

xor a1(s1,S2,aors);
xor a2(s2,s1,S1);
assign in1={S1,E1,F1};
assign in2={S2,E2,F2};


always@(posedge clk,  E1,E2,S1,S2,F1,F2,aors)
	begin
	if(en == 1)
		begin
			if(E1>E2)
				Ei=E1;
			else
				Ei=E2;

			if(E1>E2)
				e=E1-E2;
			else
				e=E2-E1;

			if(E1>E2)
				f=f2>>e;
			else
				f=f1>>e;
		end
	end

always@(*)
	begin
	if(en == 1)
		begin
		if(s2==0)
			S=S1;
		else
			begin
				if(E1>E2)
					begin
						if(f1>f)
							S=S1;
						else
							S=s1;
					end
				else
					begin
						if(f2>f)
							S=s1;
						else
							S=S1;
					end
			end
		end
	end


always@(*)
begin
	if(en == 1)
	begin
		if(s2 == 1)
			begin
				if(E1>E2)
					begin
						if(f1>f)
							Fs=f1-f;
						else
							Fs=f-f1;
					end
				else
					begin
						if(f2>f)
							Fs=f2-f;
						else
							Fs=f-f2;
					end
			end
	end
end

integer j=0;
always@(*)
begin
	if(en == 1)
	begin
		if(s2==0)
			begin
			if(E1>E2)
				Fi=f1+f;
			else
				Fi=f2+f;
			end
		else
			Fi={1'b0,Fs};
		//Normalization
		if(Fi[53] != 1'b1)
			begin
				Fi1 = Fi;
				Ei = Ei+1;
				while(Fi[53]!= 1 && j<54)
					begin
						Fi = Fi<<1;
						Ei = Ei - 1;
						j  = j+1;
					end
				j=0;
				F= Fi[52:1];
				E=Ei;
			end
		else
			begin
				Fi1 = Fi;
				F=Fi[52:1];
				E=Ei + 1;
			end
	end
end
assign out = (en) ? {S,E,F} : 64'b0;

endmodule

------------------------------------------------------------------
//Testbench

module TwoPButterfly_tb;

reg en,clk;
reg [63:0]inr1,ini1,inr2,ini2;

wire [63:0]outr1,outi1,outr2,outi2;

TwoPButterfly T1(en,clk,inr1,ini1,inr2,ini2,outr1,outi1,outr2,outi2);

always #5 clk <= ~clk;

initial
begin
	clk = 1'b0;
	en = 1'b1;

	#4
	// 7+7i , 6+6i
	inr1 <= 64'b0100000000011100000000000000000000000000000000000000000000000000;
	ini1 <= 64'b0100000000011100000000000000000000000000000000000000000000000000;
	inr2 <= 64'b0100000000011000000000000000000000000000000000000000000000000000;
	ini2 <= 64'b0100000000011000000000000000000000000000000000000000000000000000;

	#5
	//10+3i , 5+4i
	inr1 <= 64'b0100000000100100000000000000000000000000000000000000000000000000;
	ini1 <= 64'b0100000000001000000000000000000000000000000000000000000000000000;
	inr2 <= 64'b0100000000010100000000000000000000000000000000000000000000000000;
	ini2 <= 64'b0100000000010000000000000000000000000000000000000000000000000000;

end
endmodule