`define IDLE    4'b0001
`define E_0     4'b0010
`define E_1     4'b0011
`define E_2     4'b0100
`define E_3     4'b0101
`define E_4     4'b0110
`define E_5     4'b0111
`define E_6     4'b1000

module recog_seq(input clk, input rx, input [7:0] char, output reg [7:0] answer);

    reg [3:0] state;
    reg [3:0] nxt_state;

    wire [1:0] stt;


    buart asdf(.rst(1'b0), .clk(clk), .ld_tx_data(ld_tx_data), .tx_data(char_tx),
                  .tx_enable(1'b1), .tx(tx), .tx_empty(tx_empty), .uld_rx_data(uld),
                  .rx_data(char_rx), .rx_enable(1'b1), .rx(rx), .rx_empty(rx_empty),
                  .rx_err(err));

    assign stt = {(prev_state==`E_6),(state==`IDLE)};

    always @(posedge clk or posedge rst)
        if (rst) prev_state <= IDLE;
        else prev_state <= state;

    always @(*)

        case(prev_state)

            `IDLE:  state = ((char_rx == 8'h2F)&(char_tx == 8'h2F))?`E_1:prev_state;
            `E_0:       state = ((char_rx == 8'h2F)&(char_tx == 8'h2F))?prev_state:
                                  ((char_rx == 8'h5C)&(char_tx == 8'h5C))?prev_state:
                                  (char_rx == char_tx)?`E_1: `E_0;
            `E_1:       state = ((char_rx == 8'h2F)&(char_tx == 8'h2F))?`E_0:
                                  ((char_rx == 8'h5C)&(char_tx == 8'h5C))?prev_state:
                                  (char_rx == char_tx)?`E_2: `E_0;
            `E_2:       state = ((char_rx == 8'h2F)&(char_tx == 8'h2F))?`E_0:
                                  ((char_rx == 8'h5C)&(char_tx == 8'h5C))?prev_state:
                                  (char_rx == char_tx)?`E_3: `E_0;
            `E_3:       state = ((char_rx == 8'h2F)&(char_tx == 8'h2F))?`E_0:
                                  ((char_rx == 8'h5C)&(char_tx == 8'h5C))?prev_state:
                                  (char_rx == char_tx)?`E_3: `E_0;
            `E_4:       state = ((char_rx == 8'h2F)&(char_tx == 8'h2F))?`E_0:
                                  ((char_rx == 8'h5C)&(char_tx == 8'h5C))?prev_state:
                                  (char_rx == char_tx)?`E_3: `E_0;
            `E_5:       state = ((char_rx == 8'h2F)&(char_tx == 8'h2F))?`E_0:
                                  ((char_rx == 8'h5C)&(char_tx == 8'h5C))?prev_state:
                                  (char_rx == char_tx)?`E_6: `E_0;
            `E_6:       state = ((char_rx == 8'h2F)&(char_tx == 8'h2F))?`E_0:
                                  ((char_rx == 8'h5C)&(char_tx == 8'h5C))?`IDLE:
                                  (char_rx == char_tx)?`prev_state: `E_0;
            default  state = prev_state;

        endcase

    always @(*)

        if (stt==2'b11) answer = 16'h4F_4B;
        else answer = 16'h0;


endmodule