DDR stress test

C:\Users\netlab\Desktop\DDR_Stress_Tester_V1.0.2\DDR_Stress_Tester_V1.0.2\Binary
>DDR_Stress_Tester.exe -t mx6x -df scripts\MX6_series_boards\Auto_Infotainment\R
evC_and_RevB\MX6Q_ARD_DDR3_register_programming_aid_v1.5.inc
MX6DQ opened.
HAB_TYPE: DEVELOP
Image loading...
download Image to IRAM OK

Re-open MX6x device.
Running DDR test..., press "ESC" key to exit.




******************************
    DDR Stress Test (1.0.2) for MX6DQ
    Build: Dec 10 2013, 12:31:54
    Freescale Semiconductor, Inc.
******************************

=======DDR configuration==========
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 64, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used
Density per chip select: 2048MB
==================================


What ARM core speed would you like to run?
Type 0 for 650MHz, 1 for 800MHz, 2 for 1GHz, 3 for 1.2GHz
  ARM set to 1GHz

Please select the DDR density per chip select (in bytes) on the board
Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6
for 32MB
For maximum supported density (4GB), we can only access up to 3.75GB.  Type 9 to
 select this
  DDR density selected (MB): 1024


Calibration will run at DDR frequency 528MHz. Type 'y' to continue.
If you want to run at other DDR frequency. Type 'n'
  DDR Freq: 528 MHz

Would you like to run the write leveling calibration? (y/n)
  Please enter the MR1 value on the initilization script
  This will be re-programmed into MR1 after write leveling calibration
  Enter as a 4-digit HEX value, example 0004, then hit enter
0004 You have entered: 0x0004
Start write leveling calibration
Write leveling calibration completed
MMDC_MPWLDECTRL0 ch0 after write level cal: 0x001E001E
MMDC_MPWLDECTRL1 ch0 after write level cal: 0x002A001F
MMDC_MPWLDECTRL0 ch1 after write level cal: 0x0014002C
MMDC_MPWLDECTRL1 ch1 after write level cal: 0x00120027

Would you like to run the DQS gating, read/write delay calibration? (y/n)
Starting DQS gating calibration...
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BYTE 0:
        Start:           HC=0x02 ABS=0x24
        End:             HC=0x04 ABS=0x5C
        Mean:            HC=0x03 ABS=0x40
        End-0.5*tCK:     HC=0x03 ABS=0x5C
        Final:           HC=0x03 ABS=0x5C
BYTE 1:
        Start:           HC=0x02 ABS=0x18
        End:             HC=0x04 ABS=0x48
        Mean:            HC=0x03 ABS=0x30
        End-0.5*tCK:     HC=0x03 ABS=0x48
        Final:           HC=0x03 ABS=0x48
BYTE 2:
        Start:           HC=0x00 ABS=0x7C
        End:             HC=0x04 ABS=0x40
        Mean:            HC=0x02 ABS=0x5E
        End-0.5*tCK:     HC=0x03 ABS=0x40
        Final:           HC=0x03 ABS=0x40
BYTE 3:
        Start:           HC=0x01 ABS=0x6C
        End:             HC=0x04 ABS=0x48
        Mean:            HC=0x03 ABS=0x1A
        End-0.5*tCK:     HC=0x03 ABS=0x48
        Final:           HC=0x03 ABS=0x48
BYTE 4:
        Start:           HC=0x02 ABS=0x18
        End:             HC=0x04 ABS=0x60
        Mean:            HC=0x03 ABS=0x3C
        End-0.5*tCK:     HC=0x03 ABS=0x60
        Final:           HC=0x03 ABS=0x60
BYTE 5:
        Start:           HC=0x02 ABS=0x1C
        End:             HC=0x04 ABS=0x48
        Mean:            HC=0x03 ABS=0x32
        End-0.5*tCK:     HC=0x03 ABS=0x48
        Final:           HC=0x03 ABS=0x48
BYTE 6:
        Start:           HC=0x00 ABS=0x4C
        End:             HC=0x04 ABS=0x10
        Mean:            HC=0x02 ABS=0x2E
        End-0.5*tCK:     HC=0x03 ABS=0x10
        Final:           HC=0x03 ABS=0x10
BYTE 7:
        Start:           HC=0x00 ABS=0x7C
        End:             HC=0x04 ABS=0x48
        Mean:            HC=0x02 ABS=0x62
        End-0.5*tCK:     HC=0x03 ABS=0x48
        Final:           HC=0x03 ABS=0x48

DQS calibration MMDC0 MPDGCTRL0 = 0x4348035C, MPDGCTRL1 = 0x03480340

DQS calibration MMDC1 MPDGCTRL0 = 0x43480360, MPDGCTRL1 = 0x03480310

Note: Array result[] holds the DRAM test result of each byte.
      0: test pass.  1: test fail
      4 bits respresent the result of 1 byte.
      result 00000001:byte 0 fail.
      result 00000011:byte 0, 1 fail.

Starting Read calibration...

ABS_OFFSET=0x00000000   result[00]=0x11111111
ABS_OFFSET=0x04040404   result[01]=0x11111111
ABS_OFFSET=0x08080808   result[02]=0x11111111
ABS_OFFSET=0x0C0C0C0C   result[03]=0x11111111
ABS_OFFSET=0x10101010   result[04]=0x11111111
ABS_OFFSET=0x14141414   result[05]=0x11111111
ABS_OFFSET=0x18181818   result[06]=0x01011011
ABS_OFFSET=0x1C1C1C1C   result[07]=0x00011000
ABS_OFFSET=0x20202020   result[08]=0x00011000
ABS_OFFSET=0x24242424   result[09]=0x00001000
ABS_OFFSET=0x28282828   result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C   result[0B]=0x00000000
ABS_OFFSET=0x30303030   result[0C]=0x00000000
ABS_OFFSET=0x34343434   result[0D]=0x00000000
ABS_OFFSET=0x38383838   result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C   result[0F]=0x00000000
ABS_OFFSET=0x40404040   result[10]=0x00000000
ABS_OFFSET=0x44444444   result[11]=0x00000000
ABS_OFFSET=0x48484848   result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C   result[13]=0x00000000
ABS_OFFSET=0x50505050   result[14]=0x00000000
ABS_OFFSET=0x54545454   result[15]=0x00000000
ABS_OFFSET=0x58585858   result[16]=0x00000000
ABS_OFFSET=0x5C5C5C5C   result[17]=0x00100110
ABS_OFFSET=0x60606060   result[18]=0x00100111
ABS_OFFSET=0x64646464   result[19]=0x11101111
ABS_OFFSET=0x68686868   result[1A]=0x11101111
ABS_OFFSET=0x6C6C6C6C   result[1B]=0x11101111
ABS_OFFSET=0x70707070   result[1C]=0x11111111
ABS_OFFSET=0x74747474   result[1D]=0x11111111
ABS_OFFSET=0x78787878   result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C   result[1F]=0x11111111

MMDC0 MPRDDLCTL = 0x44383A3C, MMDC1 MPRDDLCTL = 0x3C3E3848

Starting Write calibration...

ABS_OFFSET=0x00000000   result[00]=0x10111111
ABS_OFFSET=0x04040404   result[01]=0x10111111
ABS_OFFSET=0x08080808   result[02]=0x10100110
ABS_OFFSET=0x0C0C0C0C   result[03]=0x10100010
ABS_OFFSET=0x10101010   result[04]=0x10100010
ABS_OFFSET=0x14141414   result[05]=0x10100010
ABS_OFFSET=0x18181818   result[06]=0x00000000
ABS_OFFSET=0x1C1C1C1C   result[07]=0x00000000
ABS_OFFSET=0x20202020   result[08]=0x00000000
ABS_OFFSET=0x24242424   result[09]=0x00000000
ABS_OFFSET=0x28282828   result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C   result[0B]=0x00000000
ABS_OFFSET=0x30303030   result[0C]=0x00000000
ABS_OFFSET=0x34343434   result[0D]=0x00000000
ABS_OFFSET=0x38383838   result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C   result[0F]=0x00000000
ABS_OFFSET=0x40404040   result[10]=0x00000000
ABS_OFFSET=0x44444444   result[11]=0x00000000
ABS_OFFSET=0x48484848   result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C   result[13]=0x00000000
ABS_OFFSET=0x50505050   result[14]=0x00000000
ABS_OFFSET=0x54545454   result[15]=0x00000000
ABS_OFFSET=0x58585858   result[16]=0x00000000
ABS_OFFSET=0x5C5C5C5C   result[17]=0x01000000
ABS_OFFSET=0x60606060   result[18]=0x01000000
ABS_OFFSET=0x64646464   result[19]=0x01001111
ABS_OFFSET=0x68686868   result[1A]=0x01001111
ABS_OFFSET=0x6C6C6C6C   result[1B]=0x01011111
ABS_OFFSET=0x70707070   result[1C]=0x01111111
ABS_OFFSET=0x74747474   result[1D]=0x11111111
ABS_OFFSET=0x78787878   result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C   result[1F]=0x11111111

MMDC0 MPWRDLCTL = 0x34363C34,MMDC1 MPWRDLCTL = 0x442C4238


   MMDC registers updated from calibration

   Read DQS Gating calibration
   MPDGCTRL0 PHY0 (0x021b083c) = 0x4348035C
   MPDGCTRL1 PHY0 (0x021b0840) = 0x03480340
   MPDGCTRL0 PHY1 (0x021b483c) = 0x43480360
   MPDGCTRL1 PHY1 (0x021b4840) = 0x03480310

   Read calibration
   MPRDDLCTL PHY0 (0x021b0848) = 0x44383A3C
   MPRDDLCTL PHY1 (0x021b4848) = 0x3C3E3848

   Write calibration
   MPWRDLCTL PHY0 (0x021b0850) = 0x34363C34
   MPWRDLCTL PHY1 (0x021b4850) = 0x442C4238


The DDR stress test can run with an incrementing frequency or at a static freq
To run at a static freq, simply set the start freq and end freq to the same valu
e
Would you like to run the DDR Stress Test (y/n)?

Enter desired START freq (135 to 672 MHz), then hit enter.
 Note: DDR3 minimum is ~333MHz, do not recommend to go too much below this.
528
  The freq you entered was: 528

Enter desired END freq (135 to 672 MHz), then hit enter.
Make sure this is equal to or greater than start freq
528
  The freq you entered was: 528

Beginning stress test



   MPDGCTRL1 PHY0 (0x021b0840) = 0x03500348
   MPDGCTRL0 PHY1 (0x021b483c) = 0x4354036C
   MPDGCTRL1 PHY1 (0x021b4840) = 0x03500318

   Read calibration
   MPRDDLCTL PHY0 (0x021b0848) = 0x463A3C40
   MPRDDLCTL PHY1 (0x021b4848) = 0x40403C4A

   Write calibration
   MPWRDLCTL PHY0 (0x021b0850) = 0x34383E32
   MPWRDLCTL PHY1 (0x021b4850) = 0x422C4436


The DDR stress test can run with an incrementing frequency or at a static freq
To run at a static freq, simply set the start freq and end freq to the same valu
e
Would you like to run the DDR Stress Test (y/n)?

Enter desired START freq (135 to 672 MHz), then hit enter.
 Note: DDR3 minimum is ~333MHz, do not recommend to go too much below this.
528
  The freq you entered was: 528

Enter desired END freq (135 to 672 MHz), then hit enter.
Make sure this is equal to or greater than start freq
528
  The freq you entered was: 528

Beginning stress test

loop: 1
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 2
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 3
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 4
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 5
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 6
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 7
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 8
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 9
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 10
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 11
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 12
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 13
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 14
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 15
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 16
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 17
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 18
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 19
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 20
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 21
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 22
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 23
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

loop: 24
DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test