prelab_2_pt2

module sevensegdecoder(input [3:0]S, output [6:0]D);
    reg [6:0] D;
    always @(S)

    case(S)
    0: D=7'b0000001;
    1: D=7'b1001111;
    2: D=7'b0010010;
    3: D=7'b0000110;
    4: D=7'b1001100;
    5: D=7'b0100100;
    6: D=7'b0100000;
    7: D=7'b0001111;
    8: D=7'b0000000;
    9: D=7'b0001100;
    10:D=7'b0001000;
    11:D=7'b1100000;
    12:D=7'b0110001;
    13:D=7'b1000010;
    14:D=7'b0110000;
    15:D=7'b0111000;
    default:D=7'b0000000;

endcase
endmodule


module FA4Bit(input[3:0]a,b, input op, output [3:0]s, output cout,ov, output [6:0]d);
    wire c1, c2, c3, y0, y1, y2, y3;
    assign y0=b[0]^op;
    assign y1=b[1]^op;
    assign y2=b[2]^op;
    assign y3=b[3]^op;

    FA fa0(a[0], y0, op, s[0], c1);
    FA fa1(a[1], y1, c1, s[1], c2);
    FA fa2(a[2], y2, c2, s[2], c3);
    FA fa3(a[3], y3, c3, s[3], cout);
        assign ov=c3^cout;
        sevensegdecoder DC(s,d);
endmodule

module FullAdder(input a,b,cin, output s, cout);
    assign s=A^b^cin;
    assign cout=(a&b) | (a&cin) | (b&cin);
endmodule


module sevensegdecoder_sim();
    reg[3:0] A,B;
    reg op;

    wire [3:0] S;
    wire cout;
    wire ov;
    wire [6:0]D;

    FA4Bit uut (A,B,op,S,cout, ov, D);

    initial begin
        A=2; B=3; op=0;
 #10    A=5; B=-3; op=0;
 #10    A=4; B=3; op=0;
 #10    A=8; B=4; op=1;
 #10    A=6; B=-2; op=1;
 #10    A=10; B=4; op=1;
 end

endmodule