INFO:  Running /home/smd/orpsoc-cores/cores/elf-loader/check_libelf.sh
INFO:  /home/smd/orpsoc-cores/build/mor1kx-generic/sim-verilator
INFO:      /home/smd/orpsoc-cores/cores/elf-loader/check_libelf.sh
/home/smd/orpsoc-cores/build/mor1kx-generic/src/verilator_tb_utils/
/home/smd/orpsoc-cores/build/mor1kx-generic/src/elf-loader/
/home/smd/orpsoc-cores/build/mor1kx-generic/sim-verilator/bench/verilator
/home/smd/orpsoc-cores/build/mor1kx-generic/src
INFO:  Verilating source

INFO:  Starting Verilator:
INFO:    Verilator working dir: /home/smd/orpsoc-cores/build/mor1kx-generic/sim-verilator
INFO:    Verilator command: /usr/bin/verilator --cc -f input.vc --top-module orpsoc_top --exe -LDFLAGS " -Wl,--start-group /home/smd/orpsoc-cores/build/mor1kx-generic/sim-verilator/verilator_tb_utils.a /home/smd/orpsoc-cores/build/mor1kx-generic/sim-verilator/elf-loader.a -Wl,--end-group -lelf " -CFLAGS -I/home/smd/orpsoc-cores/build/mor1kx-generic/src/verilator_tb_utils/ -CFLAGS -I/home/smd/orpsoc-cores/build/mor1kx-generic/src/elf-loader/ -CFLAGS -I/home/smd/orpsoc-cores/build/mor1kx-generic/sim-verilator/bench/verilator -CFLAGS -I/home/smd/orpsoc-cores/build/mor1kx-generic/src /home/smd/orpsoc-cores/build/mor1kx-generic/src/mor1kx-generic/bench/verilator/tb.cpp -Wno-fatal --trace

INFO:  /home/smd/orpsoc-cores/build/mor1kx-generic/sim-verilator
INFO:      /usr/bin/verilator --cc -f input.vc --top-module orpsoc_top --exe -LDFLAGS " -Wl,--start-group /home/smd/orpsoc-cores/build/mor1kx-generic/sim-verilator/verilator_tb_utils.a /home/smd/orpsoc-cores/build/mor1kx-generic/sim-verilator/elf-loader.a -Wl,--end-group -lelf " -CFLAGS -I/home/smd/orpsoc-cores/build/mor1kx-generic/src/verilator_tb_utils/ -CFLAGS -I/home/smd/orpsoc-cores/build/mor1kx-generic/src/elf-loader/ -CFLAGS -I/home/smd/orpsoc-cores/build/mor1kx-generic/sim-verilator/bench/verilator -CFLAGS -I/home/smd/orpsoc-cores/build/mor1kx-generic/src /home/smd/orpsoc-cores/build/mor1kx-generic/src/mor1kx-generic/bench/verilator/tb.cpp -Wno-fatal --trace
ERROR: %Error: ../src/uart16550-1.5.4/rtl/verilog/uart_transmitter.v:275: syntax error, unexpected INTEGER NUMBER, expecting IDENTIFIER or ')'
%Error: Exiting due to 1 error(s)
%Error: Command Failed /usr/bin/verilator_bin --cc -f input.vc --top-module orpsoc_top --exe -LDFLAGS ' -Wl,--start-group /home/smd/orpsoc-cores/build/mor1kx-generic/sim-verilator/verilator_tb_utils.a /home/smd/orpsoc-cores/build/mor1kx-generic/sim-verilator/elf-loader.a -Wl,--end-group -lelf ' -CFLAGS -I/home/smd/orpsoc-cores/build/mor1kx-generic/src/verilator_tb_utils/ -CFLAGS -I/home/smd/orpsoc-cores/build/mor1kx-generic/src/elf-loader/ -CFLAGS -I/home/smd/orpsoc-cores/build/mor1kx-generic/sim-verilator/bench/verilator -CFLAGS -I/home/smd/orpsoc-cores/build/mor1kx-generic/src /home/smd/orpsoc-cores/build/mor1kx-generic/src/mor1kx-generic/bench/verilator/tb.cpp -Wno-fatal --trace

ERROR: Failed to build simulation model
ERROR: "/usr/bin/verilator --cc -f input.vc --top-module orpsoc_top --exe -LDFLAGS " -Wl,--start-group /home/smd/orpsoc-cores/build/mor1kx-generic/sim-verilator/verilator_tb_utils.a /home/smd/orpsoc-cores/build/mor1kx-generic/sim-verilator/elf-loader.a -Wl,--end-group -lelf " -CFLAGS -I/home/smd/orpsoc-cores/build/mor1kx-generic/src/verilator_tb_utils/ -CFLAGS -I/home/smd/orpsoc-cores/build/mor1kx-generic/src/elf-loader/ -CFLAGS -I/home/smd/orpsoc-cores/build/mor1kx-generic/sim-verilator/bench/verilator -CFLAGS -I/home/smd/orpsoc-cores/build/mor1kx-generic/src /home/smd/orpsoc-cores/build/mor1kx-generic/src/mor1kx-generic/bench/verilator/tb.cpp -Wno-fatal --trace" exited with an error code.
ERROR: See /home/smd/orpsoc-cores/build/mor1kx-generic/sim-verilator/verilator.log for details.