`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    23:49:20 10/13/2014
// Design Name:
// Module Name:    top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top(
input clk_100,
output ser_tx,
input ser_rx
    );

    wire [7:0]  rx_data; //output of uart_rx
    reg         read_from_uart;
    reg         en_16_x_baud;
    wire    rx_data_present;
    wire    rx_full;
    wire    rx_half_full;

    wire    write_to_uart;
    wire    tx_full;
    wire    tx_half_full;


    wire [7:0] uart_status_port;
    assign uart_status_port = {3'b000,rx_data_present,rx_full,rx_half_full,tx_full,tx_half_full};


//instantiation
uart_rx receive (
        .serial_in(ser_rx),
        .data_out(rx_data),                         ////output
        .read_buffer(read_from_uart),
        .reset_buffer(1'b0),
        .en_16_x_baud(en_16_x_baud),
        .buffer_data_present(rx_data_present), //output
        .buffer_full(rx_full),                      //output
        .buffer_half_full(rx_half_full),            //output
        .clk(clk100));


uart_tx transmit (
        .data_in(rx_data/*out_port*/), //echo back rx to tx
        .write_buffer(write_to_uart),
        .reset_buffer(1'b0),
        .en_16_x_baud(en_16_x_baud),
        .serial_out(ser_tx),            //output
        .buffer_full(tx_full),          //output
        .buffer_half_full(tx_half_full),//output
        .clk(clk100));


    reg [9:0]   baud_count;

    // UART baud rate generator - 9600 baud
    always @(posedge clk100)
        if (baud_count == 651) begin
            baud_count <= 1'b0;
            en_16_x_baud <= 1'b1;
        end else begin
            baud_count <= baud_count + 1'b1;
            en_16_x_baud <= 1'b0;
        end

endmodule