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Mar 4th, 2015
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VHDL 1.35 KB | None | 0 0
  1. -------------------------------------------------------------------------------
  2. --
  3. -- Entity Name: ledbargraph
  4. -- Entity Description: Entity has an 8-bit data input bus (inp),
  5. --                     Entity also has 1 8-bit data output bus (leds)    
  6. -- Architecture Name: loop_arch
  7. -- Description: Led bargraph
  8. --                      Outputs number of 1s determined by input switch
  9. --                     For each switch that is set to 1, another led on the led bargraph lights up
  10. --                     If one switch is set to 1, the bottom led lights, if two switches are set to 1, the bottom two leds light and so on
  11. --                      Implemented using dataflow style selectors
  12. --
  13. -- Lab 04
  14. -- Section 1, Bench 8
  15. -- Author: Brian Chen and Greg Parker
  16. --
  17. -------------------------------------------------------------------------------    
  18. library ieee;
  19. use ieee.std_logic_1164.all;
  20.  
  21. entity ones_bar_graph is
  22.     port(inp : in std_logic_vector(7 downto 0);
  23.         leds : out std_logic_vector(7 downto 0));
  24. end ones_bar_graph;    
  25.  
  26. architecture loop_arch of ones_bar_graph is
  27. begin
  28.     process (inp)  
  29.     begin    
  30.         variable led_count : integer := 0;
  31.         for i in 7 downto 0 loop     
  32.             if (inp(i)) = '1' then
  33.                 led_count <= led_count + 1;
  34.             end if;
  35.         end loop;  
  36.         for j in 0 to led_count loop
  37.               leds(i) <= '1';
  38.         end loop;
  39.     end process;
  40. end loop_arch;
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