TP3 Level4

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 -- Company:
 -- Engineer:
 --
 -- Create Date:    09:55:25 11/21/2014
 -- Design Name:
 -- Module Name:    Counter - Behavioral
 -- Project Name:
 -- Target Devices:
 -- Tool versions:
 -- Description:
 --
 -- Dependencies:
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 -- Revision:
 -- Revision 0.01 - File Created
 -- Additional Comments:
 --
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 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use ieee.std_logic_unsigned.all;

 -- Uncomment the following library declaration if using
 -- arithmetic functions with Signed or Unsigned values
 use IEEE.NUMERIC_STD.ALL;

 -- Uncomment the following library declaration if instantiating
 -- any Xilinx primitives in this code.
 --library UNISIM;
 --use UNISIM.VComponents.all;

 entity Counter is
      Port ( Reset : in  STD_LOGIC;
                CLK : in  STD_LOGIC;
                S1, S2 : out  STD_LOGIC_VECTOR(25 downto 0));
 end Counter;

 architecture Behavioral of Counter is

 signal Add1, Add2 : STD_LOGIC_VECTOR(25 downto 0);
 signal Reg1, Reg2 : STD_LOGIC_VECTOR(25 downto 0);
 signal Mux1, Mux2 : STD_LOGIC_VECTOR(25 downto 0);
 signal Cmp1, Cmp2 : STD_LOGIC;

 begin

 Add1 <= Reg1 + "0000000000000000000000001";

 Mux1 <= Add1 when Cmp1 = '0' else "00000000000000000000000000" when Cmp1 = '1';

 Cmp1 <= '1' when Add1 > "0000000000000000000001000" else '0';

 Reg1 <= "00000000000000000000000000" when Reset = '0' else Mux1 when rising_edge(CLK);

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 Add2 <= Reg2 + "0000000000000000000000001";

 Mux2 <= "00000000000000000000000000" when Cmp2 = '1' and Cmp1='1' else
         Add2 when Cmp2 = '0' and Cmp1 = '1' else
            Reg2;

 Cmp2 <= '1' when Add2 > "0000000000000000000000100" else '0';

 Reg2 <= "00000000000000000000000000" when Reset = '0' else Mux2 when rising_edge(CLK);

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S1 <= Reg1;

S2 <= Reg2;

 end Behavioral;