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-- Company:
-- Engineer:
--
-- Create Date:    10:13:50 12/22/2011
-- Design Name:
-- Module Name:    biestable1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use IEEE.STD_LOGIC_ARITH.ALL;
-- use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
-- library UNISIM;
-- use UNISIM.VComponents.all;

entity biestable1 is
    Port ( suma : in  STD_LOGIC_VECTOR (15 downto 0);
           clk : in  STD_LOGIC;
              rst : in  STD_LOGIC;
           cnt : in  STD_LOGIC_VECTOR (2 downto 0);
           sumacu : out  STD_LOGIC_VECTOR (15 downto 0));
end biestable1;

architecture Behavioral of biestable1 is
begin
    process(clk, rst, cnt, suma)
    begin
        if(rst = '1') then
            sumacu <= (others => '0');
        elsif clk'event and clk = '1' then
            if(cnt = "111") then
                sumacu <= (others => '0');
            else
                sumacu <= suma;
            end if;
        end if;
    end process;
end Behavioral;