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  1. --- a/drivers/crypto/omap-aes.c 2010-09-22 16:12:40.000000000 +0200
  2. +++ b/drivers/crypto/omap-aes.c 2010-11-09 13:55:23.040243022 +0100
  3. @@ -219,6 +219,12 @@
  4.     if (dd->flags & FLAGS_ENCRYPT)
  5.         val |= AES_REG_CTRL_DIRECTION;
  6.  
  7. +#if 0
  8. +   /* it will not affect DMA error but might solve crypto issue */
  9. +   dd->ctx->flags |= FLAGS_NEW_KEY;
  10. +   dd->ctx->flags |= FLAGS_NEW_IV;
  11. +#endif
  12. +
  13.     if (dd->ctrl == val && !(dd->flags & FLAGS_NEW_IV) &&
  14.            !(dd->ctx->flags & FLAGS_NEW_KEY))
  15.         goto out;
  16. @@ -339,18 +345,6 @@
  17.         goto err_dma_out;
  18.     }
  19.  
  20. -   omap_set_dma_dest_params(dd->dma_lch_in, 0, OMAP_DMA_AMODE_CONSTANT,
  21. -                dd->phys_base + AES_REG_DATA, 0, 4);
  22. -
  23. -   omap_set_dma_dest_burst_mode(dd->dma_lch_in, OMAP_DMA_DATA_BURST_4);
  24. -   omap_set_dma_src_burst_mode(dd->dma_lch_in, OMAP_DMA_DATA_BURST_4);
  25. -
  26. -   omap_set_dma_src_params(dd->dma_lch_out, 0, OMAP_DMA_AMODE_CONSTANT,
  27. -               dd->phys_base + AES_REG_DATA, 0, 4);
  28. -
  29. -   omap_set_dma_src_burst_mode(dd->dma_lch_out, OMAP_DMA_DATA_BURST_4);
  30. -   omap_set_dma_dest_burst_mode(dd->dma_lch_out, OMAP_DMA_DATA_BURST_4);
  31. -
  32.     return 0;
  33.  
  34.  err_dma_out:
  35. @@ -458,11 +452,24 @@
  36.     omap_set_dma_dest_params(dd->dma_lch_out, 0, OMAP_DMA_AMODE_POST_INC,
  37.                  dma_addr_out, 0, 0);
  38.  
  39. -   omap_start_dma(dd->dma_lch_in);
  40. -   omap_start_dma(dd->dma_lch_out);
  41. +   /**/
  42. +   omap_set_dma_dest_params(dd->dma_lch_in, 0, OMAP_DMA_AMODE_CONSTANT,
  43. +                dd->phys_base + AES_REG_DATA, 0, 4);
  44. +
  45. +   omap_set_dma_dest_burst_mode(dd->dma_lch_in, OMAP_DMA_DATA_BURST_4);
  46. +   omap_set_dma_src_burst_mode(dd->dma_lch_in, OMAP_DMA_DATA_BURST_4);
  47. +
  48. +   omap_set_dma_src_params(dd->dma_lch_out, 0, OMAP_DMA_AMODE_CONSTANT,
  49. +               dd->phys_base + AES_REG_DATA, 0, 4);
  50. +
  51. +   omap_set_dma_src_burst_mode(dd->dma_lch_out, OMAP_DMA_DATA_BURST_4);
  52. +   omap_set_dma_dest_burst_mode(dd->dma_lch_out, OMAP_DMA_DATA_BURST_4);
  53.  
  54.     omap_aes_write_ctrl(dd);
  55.  
  56. +   omap_start_dma(dd->dma_lch_in);
  57. +   omap_start_dma(dd->dma_lch_out);
  58. +
  59.     return 0;
  60.  }
  61.  
  62. @@ -525,8 +532,6 @@
  63.  
  64.     dd->total -= count;
  65.  
  66. -   err = omap_aes_hw_init(dd);
  67. -
  68.     err = omap_aes_crypt_dma(tfm, addr_in, addr_out, count);
  69.  
  70.     return err;
  71. @@ -553,8 +558,6 @@
  72.  
  73.     omap_aes_write_mask(dd, AES_REG_MASK, 0, AES_REG_MASK_START);
  74.  
  75. -   omap_aes_hw_cleanup(dd);
  76. -
  77.     omap_stop_dma(dd->dma_lch_in);
  78.     omap_stop_dma(dd->dma_lch_out);
  79.  
  80. @@ -594,8 +597,10 @@
  81.     spin_lock_irqsave(&dd->lock, flags);
  82.     backlog = crypto_get_backlog(&dd->queue);
  83.     async_req = crypto_dequeue_request(&dd->queue);
  84. -   if (!async_req)
  85. +   if (!async_req) {
  86. +       omap_aes_hw_cleanup(dd);
  87.         clear_bit(FLAGS_BUSY, &dd->flags);
  88. +   }
  89.     spin_unlock_irqrestore(&dd->lock, flags);
  90.  
  91.     if (!async_req)
  92. @@ -678,8 +683,10 @@
  93.     err = ablkcipher_enqueue_request(&dd->queue, req);
  94.     spin_unlock_irqrestore(&dd->lock, flags);
  95.  
  96. -   if (!test_and_set_bit(FLAGS_BUSY, &dd->flags))
  97. +   if (!test_and_set_bit(FLAGS_BUSY, &dd->flags)) {
  98. +       omap_aes_hw_init(dd);
  99.         omap_aes_handle_req(dd);
  100. +   }
  101.  
  102.     pr_debug("exit\n");
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