Untitled

;
;   EVM320C243 Test Code
;   Copyright (c) 1997.
;   Spectrum Digital, Inc.
;   ALL RIGHTS RESERVED
;

;
;   This is a modification of the boot routine V6.60 from the TI run time
;   support library. This was chosen as a starting point because TI
;   split the C5x and 2x/2xx combination.
;

;
;
;   This module contains the following definitions :
;
;         __stack    - Stack memory area
;         _c_int0    - Boot function
;         _var_init  - Function which processes initialization tables
;
;
        .include    LF240x.h  ; hier die pripherieadressen für asm-prog klein geschrieben

	.global  _c_int0, cinit
	.global  _main, _abort
	.global .bss, end


WD_CNTR 	.set	07023h		;WD Counter reg
WD_KEY		.set	07025h		;WD Key reg
WD_CNTL 	.set	07029h		;WD Control reg

scsr1  		.set	07018h
dp7000  	.set 224            ;page 1 of peripheral file (7000h/80h)

WSGR		.set	0FFFFh		;Wait State Generator Register


;-----------------------------------------------------------------------------
; Debug directives
;-----------------------------------------------------------------------------
		.def	GPR0			;General purpose registers.
		.def	GPR1
		.def	GPR2
		.def	GPR3


;-----------------------------------------------------------------------------
; Variable Declarations for on chip RAM Blocks
;-----------------------------------------------------------------------------
		.bss	GPR0,1		;General purpose registers.
		.bss	GPR1,1
		.bss	GPR2,1
		.bss	GPR3,1
		.bss	REG5,1
		.bss	REGA,1


;-----------------------------------------------------------------------------
; M A C R O - Definitions
;-----------------------------------------------------------------------------
SBIT0		.macro	DMA, MASK	;Clear bit Macro
		LACC	DMA
		AND	#(0FFFFh-MASK)
		SACL	DMA
		.endm

SBIT1		.macro	DMA, MASK	;Set bit Macro
		LACC	DMA
		OR	#MASK
		SACL	DMA
		.endm

kickdog		.macro			;Watchdog reset macro
		LDP	#00E0h
		SPLK	#05555h, WD_KEY
		SPLK	#0AAAAh, WD_KEY
		LDP	#0h
		.endm


;
; CONST COPY OPTION
; If your system cannot support allocating an initialized section to data
; memory, and you want the boot routine to copy .const from program to
; data memory, then set this CONST_COPY variable to 1
;
; Note the code that does the copy depends on you having the following
; in your linker command file
;
;       MEMORY
;       {
;         PAGE 0 : PROG : ...   /* 'PROG' AND 'DATA' ARE EXAMPLE NAMES */
;         PAGE 1 : DATA : ...
;         ...
;       }
;
;       SECTIONS
;       {
;         ...
;         .const : load = PROG PAGE 0, run = DATA PAGE 1
;                  {
;                    __const_run = . ;
;                    *(.c_mark)
;                    *(.const)
;                    __const_length = . - __const_run;
;                  }
;         ...
;       }
;
CONST_COPY	.set	0

;
; For CONST COPY, Define the load address of the .const section
; depends on linker command file being written as above
;
	.if     CONST_COPY
	.sect   ".c_mark"
	.label  __const_load

	.global __const_run, __const_length

	.text
	.endif ; CONST_COPY

;
; Declare the stack.  Size is determined by the linker option -stack
;
__stack:        .usect  ".stack",0

;
; FUNCTION DEF : _c_int0
;
;   1) Set up stack
;   2) Set up proper status
;   3) If "cinit" is not -1, init global variables
;   4) call users' program
;
;
;
_c_int0:                            ; entry point from reset vector

       SETC    INTM                 ;Disable interrupts
;
; Initialize status bit fields *NOT* initialized at reset
;
       CLRC    XF                   ; turn off xf bit
       CLRC    SXM                  ;Clear Sign Extension Mode
       CLRC    OVM                  ;Reset Overflow Mode
       CLRC    CNF                  ;Config Block B0 to Data mem.

       LDP     #0E0h
       SPLK    #006Fh,WD_CNTL
       kickdog
	   LDP     #00E0h


;		ldp		#mcra >> 7 ; der org.-code nimmt GPR3 ist bei def. von ram vor main aber nicht sicher zuerreichen
;       	SPLK    #4h,mcra
;       	OUT     mcra,WSGR ;Set XMIF to run w/no(0) wait states
;       	SPLK    #0h,mcra  ; mcra zurück in den resetzustand

		ldp		#dp300  ; der org.-code nimmt GPR3 ist bei def. von ram vor main aber nicht sicher zuerreichen
       	SPLK    #0h,0	; 0x300
       	OUT     0,WSGR  ; 0x300 nach WSGR Set XMIF to run w/no(0) wait states

	nop
	LDP 	#dp7000
	lacl	scsr1
;
;Set PLL for x4 mode
;            5432109876543210
	and		#1111000111111111b
	sacl	scsr1

	LDP		#padatdir >> 7
	lacl	padatdir
	;        7654321076543210
	or		#0000010000000000b			; iopa2 auf ausgang laufzeitmessung
	sacl	padatdir

lauf:
	LDP		#padatdir >> 7
	lacl	padatdir
	;        7654321076543210
	and		#1111111111111011b			; iopa2 auf ausgang laufzeitmessung
	sacl	padatdir
	lacl	padatdir
	or		#bit2
	sacl	padatdir
;	b		lauf

	call	clrram60h  ; 60-iger Bereich auf Null
	call	clrram300h ; 300-iger Bereich auf Null
	call	clrram200h ; 200-iger Bereich auf Null
	call	clrram800h ; 800-iger Bereich auf Null

;	call	initpwmA   ; init PWM-A
;	call	initpwmB   ; init PWM-B
;	call	initadc    ; init Analog-Digi.-Wandler
;
;  Set up initial stack and frame pointers
;
	LRLK    AR0,__stack             ; set up frame pointer
	LRLK    AR1,__stack             ; set up stack pointer

;
; Initialize status bit fields which are set to these same values by reset.
; If you run this routine from reset, you can comment out this code.
;
		SPM     0                       ; product shift count of zero
        MAR     *,AR0                   ; AR = 0, mls 10/07/96

		SSXM                            ; set SXM=1 for next instruction
;
; If cinit is not -1, process initialization tables
;
	LALK    cinit                   ; get pointer to init tables
	ADDK    1
	BZ      skip                    ; if (cinit == -1)

	CALL    _var_init,AR1           ; var_init()

;
;  Call the user's program
;
skip:
	.if     CONST_COPY
	CALL    const_copy
	.endif

                           ; start of hw stack init code
        LACK    #0014h     ; vectors for underflow
        SACL    *
        PSHD    *
        PSHD    *
        PSHD    *
        PSHD    *
        PSHD    *
        PSHD    *
        PSHD    *
        PSHD    *

	CALL    _main,AR1
	CALL    _abort,AR1              ; to never return...

	.page

; setze ram auf Null

clrram60h ; 32 worte
	lar	ar1,#60H  ;begin des ram nach ar1
	mar	*,ar1	; arp mit ar1 laden
	lac	#0  	;accu auf null
	rptk	31	; 31 mal speichen von accu mit increment
	sacl	*+      ; 32-ste mal
	ret

clrram300h ; 255 worte
	lar	ar1,#300H	; begin des ram nach ar1
	mar	*,ar1		; arp mit ar1 laden
	lac	#0  		; accu auf null
	rptk	255		; 255 mal speichen von accu mit increment
	sacl	*+
	ret

clrram200h ; 255 worte
	lar	ar1,#200H	; begin des ram nach ar1
	mar	*,ar1		; arp mit ar1 laden
	lac	#0  		; accu auf null
	rptk	255		; 255 mal speichen von accu mit increment
	sacl	*+
	ret
clrram800h ; 2048 worte
	lar	ar1,#800H	; begin des ram nach ar1
	mar	*,ar1		; arp mit ar1 laden
	lacl	#2048
c800	push
	kickdog
	lac	#0  		; accu auf null
	sacl	*+
	pop
	sub 	#1
	bcnd	c800,neq
	nop
	nop
	ret


;----------------------------------------------------
; Init ADC registers
;---------------------------------------------------
initadc
       ldp      #dp7000
       lacl     scsr1
       or       #0000000010000000b ; Enable clock to ADC module
       sacl     scsr1
       LDP      #dp7080;0E1h
       SPLK     #0100000000000000b,adctrl1 ; Reset ADC module
       nop
       nop
       SPLK     #0011000100010000b,adctrl1 ; Take ADC out of reset
;                ||||||||||||||||
;                5432109876543210
; bit 15  RSVD |
; bit 14  Reset(1) |
; bit 13,12  Soft & Free
; bit 11->8	0001 = 385 Ohm Acq.prescalers
; bit 7  	   0    Clock prescaler
; bit 6  Cont.run (1)
; bit 5  Int.priority (Hi.0)
; bit 4  Seq.casc (0dual)
; Setup a maximum of 16 conversions
;     SPLK      #15,max_conv ; Setup for 16 conversions
; Setup of 5 conversions
; adc0 x1=y aus Reihenschwingkreis;
; adc1 x2   aus Reihenschwingkreis
; adc2 Y1 aus Zweigrößemregelung
; adc3 Y2 aus Zweigrößemregelung
; adc4 sollwertsprung zwischen 1,988 und 1,25 Volt
      SPLK      #4,max_conv ; Setup for 5 conversions

; Program the conversion sequence. This is the sequence of channels that will
; be used for the 16 conversions.
      SPLK      #03210h, chselseq1 ; Convert Channels 0,1,2,3
      SPLK      #07654h, chselseq2 ; Convert Channels 4,5,6,7
      SPLK      #0BA98h, chselseq3 ; Convert Channels 8,9,10,11
      SPLK      #0FEDCh, chselseq4 ; Convert Channels 12,13,14,15

	ret


;=====================================================================
;  init PWM AAAAAAAAAAAAAAAAAAAAAAAA
; achtung gptcona wird nicht beruehrt
;=====================================================================
initpwmA:

; switch on EVA
	LDP 	#dp7000
	lacl	scsr1
;                5432109876543210
    or      #0000000000000100b
	SACL	scsr1

	LDP     #dp7080	;DP-->7080h-70FFh
	lacl	mcra	;Set IOPA pins and IOPB pins Seite 5-6
			;to primary function for pwm.
;                5432109876543210
	or	#0000111111000000b  ;
	sacl	mcra


	LDP		#dp7400
; Initialize counter registers
	SPLK	#00000H,t1cnt	;7401h GP Timer 1 counter

;----------------------------------------------------------------------
; init PWM The following section of codes initializes asymmetric PWM with
; dead band  Configure ACTRA
;-----------------------------------------------------------------------
	 ldp	   #dp7400
;

       SPLK      #0000011001100110b,actra ; neg bei label
;                 ||||||||||||||||  gopwm4 darf nicht aktiv sein
;                 5432109876543210
;
* bit	15	0	SV rotation direction (for here not applicable)
* bits 14-12	000	Space vector bits (for here not applicable)
* bits 11-10	01	PWM6 active low
* bits 9-8	10	PWM5 active high
* bits 7-6	10	PWM4 active low
* bits 5-4	01	PWM3 active high
* bits 3-2	01	PWM2 active low
* bits 1-0	10	PWM1 active high
;


;--------------------------------------------------------------------
; init PWM Configure DBTCONA
;-----------------------------------------------------------------------
        ldp      #dp7400
;        SPLK     #0000000111100100b,dbtcona ; fuer IGBT-Treiber
        SPLK     #0000011111100100b,dbtcona ; totzeit
        SPLK     #0000000111100000b,dbtcona ; totzeit
;        SPLK     #0000111111100100b,dbtcona ; totzeit
;                 ||||||||||||||||
;                 5432109876543210
; bit  15-12 reserved
;
; bit 7	      1 dead-band timer 3 enable  PWM5 und 6
; bit 6	      1	dead-band timer 2 enable  PWM3 und 4
; bit 5       1 dead-band timer 1 enable  PWM1 und 2
; bit 4-2   001 dead-band timer prescaler 000 x/1 001 x/2 010 x/4 011 x/8
; bit 1-0 		reserved
; bit  4-2 001
; bit 11-8 1111 1   uSek tot
; bit 11-8 0001 100 nSek tot
; bit 11-8 1000 0,6 uSek tot
; bit 11-8 1111 1uSek tot
; bit 11-8 0111
; eupec-modul bei 0001 ca. 43°c gemessen nachgeben des bef14
; 0111 gewählt. Bei 0000 steig dei temp deutlich
; für IXYS  0100
; temperaturen an den HARRIS-IGBTs bei verschiederenen totzeiten
; gemessen wurde ohne Last, Positiooniert bei 20°C Raumtemperatur
; im schraubloch des IGBTS neben dem Shopper IGBT
; totzeit 0111 35.1°C
; totzeit 0100 36.9°C
; totzeit 0000 41.2°C
; Initialize period registers
        ldp     #dp7400
        SPLK    #64000,t1per	; this is the period of pwm !!!!

; Initialize compare registers for 50% duty cycle, about 25KHz frequency
	SPLK	#3,cmpr1	;7417h F. Comp U 1 compare value
	SPLK	#3,cmpr2	;7418h F. Comp U 2 compare value
	SPLK	#3,cmpr3	;7419h F. Comp U 3 compare value

;-----------------------------------------------------------------------------
; init PWM initialize comcona registers
;----------------------------------------------------------------------
;
	ldp	#dp7400
        SPLK    #1100100000000000b,comcona ;7411h
;                5432109876543210
; bit 15	 1	enable compare aktion
; bit 14-13 10  immediate reload condition ?????? 01 00
; bit 12     0  space vektor disbale
; bit 11-10 10  immediate actionreg reload condition ??????? 01 00
; bit 9      0  PWMout in high impedance
; bit 8-0   --	reseviert
;
;----------------------------------------------------------------
; Configure T1CON and start GP Timers 1
	ldp	#dp7400
	splk	#1100111101000110b,t1con
;                FEDCBA9876543210
;  f-e  01  nach emulatorstopp mache weiter bis zum compare.
;           Damit werden die ausgaenge auf def. Zustand gebracht
;   D   -------------
;  c-b  10  contin. up count for asym. waveform
;  c-b  01  contin  up/down-count for sym. pwm-waveform
;  a-8  000 inputclock pre = 128
;  7    0   use own tenable bit
;  6    0   tenable achtng bit 6 wird am schluss von intall gesetzt
;  5-4  00  clock source intern
;  3-2  00  timer compare reg reload ??????????? vergkl. mit copmare
;    1   1  enable timer compare
;    0   0  use own  period register
;    b		initall
; !!!!!!!!!! PWM AAAAAAAAA is now running wenn in comcona bit 9=1 gestzt wird !!!!!!!!!!
;	b	$+0
	ret

;=====================================================================
;  init PWM BBBBBBBBBBBBBBBBBBBBB
;=====================================================================
initpwmB:

; switch on EVB
	LDP 	#dp7000
	lacl	scsr1
;                5432109876543210
        or      #0000000000001000b
	SACL	scsr1

	LDP     #dp7080	;DP-->7080h-70FFh
	lacl	mcrc	;Set only IOPE4 PWM10 und IOPE6 PWM12 !!!! Seite 5-8
			;to primary function for pwm.
;                5432109876543210
	or	#0000000001010000b  ;
	sacl	mcrc

	LDP	#dp7500
; Initialize counter registers
	SPLK	#00000H,t3cnt	;

;----------------------------------------------------------------------
;init PWM The following section of codes initializes asymmetric PWM with
; dead band  Configure ACTRB
;-----------------------------------------------------------------------
	 ldp	   #dp7500
; in diesem Fall gibt es in der drehzahlregelung kein anderes
; als bei dem fall, wenn neg bei hopwm4 aktiv ist (bei kleinen
; drehzahlen kein unterschied. der unterschied ist das mit neg
; aktiv mehr energie zurueckgespeist wird, waehrend im anderen fall
; die bremsenergie in den igbts umgesetzt wird
;         SPLK      #0000011010010110b,actrb ; neg bei label
;                   ||||||||||||||||   gopwm4 muss aktiv sein
;                   5432109876543210
;
* bit	15	0	SV rotation direction (for here not applicable)
* bits 14-12	000	Space vector bits (for here not applicable)
* bits 11-10	01	PWM6 active low
* bits 9-8	10	PWM5 active high
* bits 7-6	10	PWM4 active high
* bits 5-4	01	PWM3 active low
* bits 3-2	01	PWM2 active low
* bits 1-0	10	PWM1 active high
;

       SPLK      #0000011001100110b,actrb ; neg bei label
;                 ||||||||||||||||  gopwm4 darf nicht aktiv sein
;                 5432109876543210
;
* bit	15	0	SV rotation direction (for here not applicable)
* bits 14-12	000	Space vector bits (for here not applicable)
* bits 11-10	01	PWM6 active low
* bits 9-8	10	PWM5 active high
* bits 7-6	10	PWM4 active low
* bits 5-4	01	PWM3 active high
* bits 3-2	01	PWM2 active low
* bits 1-0	10	PWM1 active high
;


;--------------------------------------------------------------------
; init PWM Configure DBTCONB
;-----------------------------------------------------------------------
        ldp      #dp7500
;        SPLK     #0000000111100100b,dbtcona ; fuer
        SPLK     #0000000111100100b,dbtconb ; totzeit fuer amtec-treiber
;                 ||||||||||||||||
;                 5432109876543210
; bit  5-2 		reserved
; bit  1-8 1111	periode dead-band timers
; bit 7	      1 dead-band timer 3 enable  PWM11und 12
; bit 6	      1	dead-band timer 2 enable  PWM9 und 10
; bit 5       1 dead-band timer 1 enable  PWM7 und 8
; bit 4-2   001 dead-band timer prescaler
; bit 1-0 		reserved
; bit  4-2 001
; bit 11-8 1111 1   uSek tot
; bit 11-8 0001 100 nSek tot
; bit 11-8 1000 0,6 uSek tot
; bit 11-8 1111 1uSek tot

; Initialize period registers
        ldp     #dp7500
        SPLK    #1024,t3per	; this is the period of pwm !!!!
; 25nSek * 1024 = 39,625 kHz Grundfrequenz
; auflösung 10 bit
; Initialize compare registers for 50% duty cycle, about 25KHz frequency
	SPLK	#512,cmpr4	;7517h F. Comp U 1 compare value
	SPLK	#512,cmpr5	;7518h F. Comp U 2 compare value
	SPLK	#512,cmpr6	;7519h F. Comp U 3 compare value

;-----------------------------------------------------------------------------
; init PWM initialize comconb registers
;----------------------------------------------------------------------
;
	ldp	#dp7500
        SPLK    #1100101000000000b,comconb ;
;                FEDCBA9876543210
; bit F		 1	enable compare aktion
; bit E-D   10  immediate reload condition ?????? 01 00
; bit C      0  space vektor disbale
; bit B-A   10  immediate actionreg reload condition ??????? 01 00
; bit 9      0  PWMout in high impedance
; bit 8-0   --	reseviert
;
;----------------------------------------------------------------
; Configure T1CON and start GP Timers 1
	ldp	#dp7500
	splk	#1101000001000110b,t3con
;                FEDCBA9876543210
;  f-e  01  nach emulatorstopp mache weiter bis zum compare.
;           Damit werden die ausgaenge auf def. Zustand gebracht
;   D   -------------
;  c-b  10  contin up count
;  a-8  000 inputclock pre =0
;  7    0   use own tenable bit
;  6    0   tenable achtng bit 6 wird am schluss von intall gesetzt
;  5-4  00  clock source intern
;  3-2  00  timer compare reg reload ??????????? vergkl. mit copmare
;    1   1  enable timer compare
;    0   0  use own  period register
;    b		initall
; !!!!!!!!!! PWMBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB ist now runing

	ret


;
;  FUNCTION DEF : _var_init
;
;  PROCESS INITIALIZATION TABLES.  TABLES ARE IN
;  PROGRAM MEMORY IN THE FOLLOWING FORMAT :
;
;       .word  <length of init data in words>
;       .word  <address of variable to initialize>
;       .word  <init data>
;       .word  ...
;
;  The init table is terminated with a zero length
;
;

_var_init:

;
; C2xx Version
;
	ADRK    2                       ; allocate two words of local memory
	LALK    cinit                   ; load accumulator with base of table
	LARP    AR0

;
;  Read init record header.
;  An init record with a zero length terminates the list.
;
loop:
	TBLR    *+                      ; read length
	ADDK    1
	TBLR    *                       ; read address

	LAR     AR2,*-                  ; load variable address into ar2
	LAR     AR3,*,AR3               ; load count into ar3
	BANZ    copy,*-,AR2             ; check for end of table

;
;  At end of list, return to caller
;
	LARP    AR1
	SBRK    2                       ; deallocate locals
	RET                             ; return to _c_int0

;
;  Perform the copy of data from program to data
;
copy:
	ADDK    1                       ; increment pointer to data
	TBLR    *+,AR3                  ; copy data from program to variable
	BANZ    copy,*-,AR2             ; until count is zero

	ADDK    1                       ; point to beginning of next record
	B       loop,AR0                ; go process next record


	.page

;
; CONST COPY Routine - copies the .const section from program to data memory
;
	.if CONST_COPY
const_copy:

;
; C2xx version - must use 'RPT *' because RPTK count isn't big enough
;
	LALK    #__const_length         ; load length of const section
	BZ      quit                    ; if 0, quit
	LRLK    AR2,#__const_run        ; AR2 = const address in data
	LALK    #__const_length-1       ; load length - 1
	SACL    *                       ; write to temp

	RPT     *,AR2                   ; repeat length times
	BLKP    #__const_load,*+        ; block copy from program

	LARP    AR1                     ; restore ARP to SP
quit:
	RET                             ; return

	.endif ; CONST_COPY

	.end