API tools faq
paste
Advertisement
Guest User

neopixelsglittereffect

a guest
Nov 23rd, 2016
189
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
MPASM 9.22 KB | None | 0 0
raw download clone embed print report
  1.  
  2. ; PIC18F2550 Configuration Bit Settings
  3.  
  4. ; ASM source line config statements
  5.  
  6. #include "p18F2550.inc"
  7.  
  8. ; CONFIG1L
  9.   CONFIG  PLLDIV = 2            ; PLL Prescaler Selection bits (Divide by 2 (8 MHz oscillator input))
  10. ;  CONFIG  CPUDIV = OSC1_PLL2    ; System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
  11.   CONFIG  CPUDIV = OSC4_PLL6    ; System Clock Postscaler Selection bits ([Primary Oscillator Src: /4][96 MHz PLL Src: /6])
  12.   CONFIG  USBDIV = 2            ; USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes from the 96 MHz PLL divided by 2)
  13.  
  14. ; CONFIG1H
  15.   ;CONFIG  FOSC = INTOSCIO_EC    ; Oscillator Selection bits (Internal oscillator, port function on RA6, EC used by USB (INTIO))
  16.   CONFIG  FOSC = HSPLL_HS       ; Oscillator Selection bits (HS oscillator, PLL enabled (HSPLL))
  17.   CONFIG  FCMEN = OFF           ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
  18.   CONFIG  IESO = OFF            ; Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
  19.  
  20. ; CONFIG2L
  21.   CONFIG  PWRT = OFF            ; Power-up Timer Enable bit (PWRT enabled)
  22.   CONFIG  BOR = OFF             ; Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
  23.   CONFIG  BORV = 3              ; Brown-out Reset Voltage bits (Minimum setting 2.05V)
  24.   CONFIG  VREGEN = OFF          ; USB Voltage Regulator Enable bit (USB voltage regulator disabled)
  25.  
  26. ; CONFIG2H
  27.   CONFIG  WDT = OFF             ; Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
  28.   CONFIG  WDTPS = 32768         ; Watchdog Timer Postscale Select bits (1:32768)
  29.  
  30. ; CONFIG3H
  31.   CONFIG  CCP2MX = OFF          ; CCP2 MUX bit (CCP2 input/output is multiplexed with RB3)
  32.   CONFIG  PBADEN = OFF          ; PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
  33.   CONFIG  LPT1OSC = OFF         ; Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
  34.   CONFIG  MCLRE = OFF           ; MCLR Pin Enable bit (RE3 input pin enabled; MCLR pin disabled)
  35.  
  36. ; CONFIG4L
  37.   CONFIG  STVREN = ON           ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
  38.   CONFIG  LVP = OFF             ; Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
  39.   CONFIG  XINST = OFF           ; Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode enabled)
  40.  
  41. ; CONFIG5L
  42.   CONFIG  CP0 = OFF             ; Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)
  43.   CONFIG  CP1 = OFF             ; Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)
  44.   CONFIG  CP2 = OFF             ; Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)
  45.   CONFIG  CP3 = OFF             ; Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)
  46.  
  47. ; CONFIG5H
  48.   CONFIG  CPB = OFF             ; Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)
  49.   CONFIG  CPD = OFF             ; Data EEPROM Code Protection bit (Data EEPROM is not code-protected)
  50.  
  51. ; CONFIG6L
  52.   CONFIG  WRT0 = OFF            ; Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)
  53.   CONFIG  WRT1 = OFF            ; Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)
  54.   CONFIG  WRT2 = OFF            ; Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)
  55.   CONFIG  WRT3 = OFF            ; Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)
  56.  
  57. ; CONFIG6H
  58.   CONFIG  WRTC = OFF            ; Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)
  59.   CONFIG  WRTB = OFF            ; Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)
  60.   CONFIG  WRTD = OFF            ; Data EEPROM Write Protection bit (Data EEPROM is not write-protected)
  61.  
  62. ; CONFIG7L
  63.   CONFIG  EBTR0 = OFF           ; Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)
  64.   CONFIG  EBTR1 = OFF           ; Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)
  65.   CONFIG  EBTR2 = OFF           ; Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)
  66.   CONFIG  EBTR3 = OFF           ; Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)
  67.  
  68. ; CONFIG7H
  69.   CONFIG  EBTRB = OFF           ; Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)
  70.  
  71.  
  72.  
  73. RES_VECT  CODE    0x0000            ; processor reset vector
  74.     GOTO    START                   ; go to beginning of program
  75.  
  76. ; TODO ADD INTERRUPTS HERE IF USED
  77.  
  78.  
  79. ;DELAY EQU H'0000'
  80. TIMERH EQU 0x63
  81. TIMERL EQU 0xc0
  82.  
  83. _mybank1 UDATA 0x0060
  84. DELAY res 1
  85. DELAY2 res 1
  86. LSR res D'3'
  87. LSRG res D'2' ; memory for the Galois LFSR
  88. R1 res 1
  89. R2 res 1
  90. R3 res 1
  91. PIXELS res 48
  92. timer res 1
  93.  
  94.  
  95. MAIN_PROG CODE                      ; let linker place main program
  96.  
  97. START
  98.    
  99.     ;movlw B'01110010' ; 8 MHz INTOSCIO
  100.     ;movwf OSCCON
  101.     ;movlw B'00001111' ; tune it up to max
  102.     ;movwf OSCTUNE
  103.     CLRF PORTA
  104.     CLRF PORTB
  105.     CLRF PORTC
  106.     CLRF LATA
  107.     bcf UCON,3
  108.     bsf UCFG,3
  109.     MOVLW 0Fh
  110.     MOVWF ADCON1
  111.     MOVLW 07h
  112.     MOVWF CMCON
  113.     MOVLW 00h
  114.     MOVWF TRISA
  115.     MOVWF TRISB
  116.     MOVWF TRISC
  117.     movlw B'10000000'
  118.     movwf T0CON
  119.     movlw TIMERH
  120.     movwf TMR0H
  121.     movlw TIMERL
  122.     movwf TMR0L
  123.     bcf INTCON,TMR0IE
  124.     bcf INTCON,TMR0IF
  125.     MOVLW 01h
  126.     MOVWF LSR
  127.     MOVLW 00h
  128.     MOVWF LSR+1
  129.     movlw B'00001000'
  130.     movwf LSR
  131.     movwf LSR+1
  132.     movwf LSR+2
  133.     movwf LSRG
  134.     movwf LSRG+1
  135.     movlw 0x10
  136.     movwf timer
  137.    
  138. MAIN
  139.     ;call CLRPIXELS
  140.     call FADEPIXELS
  141.     decf timer
  142.     bnz _SKIP
  143.     movlw 0x10
  144.     movwf timer
  145.     call LFSR_EXTERNAL
  146.     call TO_PORTS
  147.     btfsc LSR,7
  148.     goto _SKIP
  149.     ;movf LSR,0
  150.     call LFSR_EXTERNAL
  151.     call LFSR_INTERNAL
  152.     call TO_PORTS
  153.     call PUTPIXEL
  154. _SKIP
  155.     call UpdateNeoPixels_x16
  156.     call WaitForTimer
  157.     goto MAIN
  158.  
  159. WaitForTimer
  160.     btfss INTCON,TMR0IF
  161.     goto WaitForTimer
  162.     bcf INTCON,TMR0IF
  163.     movlw TIMERH
  164.     movwf TMR0H
  165.     movlw TIMERL
  166.     movwf TMR0L
  167.     return
  168.    
  169. LFSR_EXTERNAL
  170. ; Fibonacci
  171. ; ab-cd--- ; the taps a,b,c,d
  172. ; -ab-cd-- ; shifted right to align
  173. ; -x--y--- ; bitwise xor'ed
  174. ; ----x--y ; shifted right three times
  175. ; ----z--- ; bitwise xor'ed again, move this bit to carry
  176.     rrcf LSR+2,0 ; rotate and store in WREG
  177.     xorwf LSR+2,0 ; xor wreg->wreg
  178.     movwf R1      ; move it to r1, keep wreg intact
  179.     rrcf R1       ; rotate x3
  180.     rrcf R1
  181.     rrcf R1
  182.     xorwf R1     ; xor old wreg with R1.
  183.     bcf STATUS,C ; clear carry flag
  184.     btfss R1,3   ; bit test file (R1 bit3) skip if set
  185.     goto SHIFT   ;
  186.     bsf STATUS,C ; set carry flag (only if R1 bit3 is set)
  187. SHIFT
  188.     ; rotate the 24bit shiftregister using carry
  189.     rlcf LSR
  190.     rlcf LSR+1
  191.     rlcf LSR+2
  192.     return
  193.  
  194. LFSR_INTERNAL
  195.  ;Galois LFSR, 16 bit
  196.  ;[16, 15, 13, 4] taps
  197.     bcf STATUS,C
  198.     rlcf LSRG
  199.     rlcf LSRG+1 ; feedback enters carry
  200.     bc LFSR_INTERNAL_1
  201.     return
  202. LFSR_INTERNAL_1
  203.     movlw B'00001000' ; mask high byte
  204.     xorwf LSRG+1
  205.     movlw B'00001011'; mask low byte
  206.     xorwf LSRG
  207.     return
  208.  
  209. TO_PORTS
  210.         ; to ports
  211.     movlw B'11111110'
  212.     andwf LSR,0
  213.     movwf LATA
  214.     ;movff LSR,LATA
  215.     movff LSR+1,LATB
  216.     movff LSR+2,LATC
  217.     return
  218.    
  219. PUTPIXEL
  220.     movf LSR,0
  221.     ;xorlw LSRG
  222.     xorwf LSRG,0
  223.     andlw B'00001111'
  224.     movwf R1
  225.     addwf R1,0
  226.     addwf R1,0
  227.     addlw PIXELS
  228.     clrf FSR0H
  229.     movwf FSR0L
  230. ;    lfsr FSR0, R1
  231.     movlw 0x00
  232.     btfsc LSR,4
  233.     movlw 0x60
  234.     movwf POSTINC0
  235.     movlw 0x00
  236.     btfsc LSR,5
  237.     movlw 0x60
  238.     movwf POSTINC0
  239.     movlw 0x00
  240.     btfsc LSR,6
  241.     movlw 0x60
  242.     movwf POSTINC0
  243.     return
  244.    
  245. UpdateNeoPixels_x16
  246. ; changes R1, R2 and R3
  247.     ;movlw 0x99
  248.     ;movwf PIXELS
  249.     movlw 48
  250.     movwf R3 ; bytecounter
  251.     lfsr FSR0, PIXELS
  252. UNP_NEXT_SUBPIXEL
  253.     movlw 8
  254.     movwf R2 ; bitcounter
  255.     ;movf POSTINC0,0
  256.     ;movwf R1 ; pixeldata
  257.     movff POSTINC0,R1
  258. UNP_NEXT_BIT
  259.     rlcf R1 ; rotate last bit into carry
  260.     bnc UNP_WRITEL
  261. UNP_WRITEH
  262.     bsf PORTA,0
  263.     nop
  264.     nop
  265.     bcf PORTA,0
  266.     decfsz R2
  267.     goto UNP_NEXT_BIT
  268.     decfsz R3
  269.     goto UNP_NEXT_SUBPIXEL
  270.     return
  271. UNP_WRITEL
  272.     bsf PORTA,0
  273.     bcf PORTA,0
  274.     nop
  275.     nop
  276.     decfsz R2
  277.     goto UNP_NEXT_BIT
  278.     decfsz R3
  279.     goto UNP_NEXT_SUBPIXEL
  280.     return
  281.  
  282. WriteL
  283.     bsf PORTA, 0
  284.     bcf PORTA, 0
  285.     nop
  286.     nop
  287.     nop
  288.     nop
  289.     return
  290.  
  291. WriteH
  292.     bsf PORTA, 0
  293.     nop
  294.     nop
  295.     bcf PORTA, 0
  296.     nop
  297.     nop
  298.     return
  299.  
  300. FADEPIXELS
  301.     movlw d'48'
  302.     movwf R1 ; byte counter
  303.     bcf STATUS,C
  304.     lfsr FSR0, PIXELS
  305. FP_NEXT
  306.     ;rrncf INDF0
  307.     ;bcf POSTINC0,7
  308.     movlw 0x00
  309.     cpfseq INDF0
  310.     decf INDF0
  311.     incf FSR0L
  312.     decfsz R1
  313.     goto FP_NEXT
  314.     return
  315.    
  316. CLRPIXELS
  317.     movlw d'48'
  318.     movwf R1
  319.     lfsr FSR0, PIXELS
  320. CP_NEXT
  321.     clrf POSTINC0
  322.     decfsz R1
  323.     goto CP_NEXT
  324.     return
  325.  
  326.     END
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!