audio

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;


entity filter    is
    port(   CLOCK_50,reset                      :in std_logic;
            read_ready, write_ready             :in std_logic;
            read_s,write_s                      :out std_logic;
            readdata_left, readdata_right       :in std_logic_vector(23 downto 0);
            writedata_left, writedata_right     :out std_logic_vector(23 downto 0));
end filter;

architecture struktur of filter is

-- Specify the signals you want to use.
-- Draw a schematic first!
    type tilstander is (s0,s1,s2,s3);
    signal tilstand, neste                  : tilstander;
    signal s_filter_ready                   : std_logic;
    signal s_write, s_read, s_filter        : std_logic;
    signal s_read_left, s_read_right    : std_logic_vector(23 downto 0);
    signal s_write_left, s_write_right  : std_logic_vector(23 downto 0);
    signal s_akkl, s_akkr                   : std_logic_vector(23 downto 0);

    constant divider : integer := 3;
    constant fifo_length : integer := 2** divider;
    type fifo_type is array (fifo_length -1 downto 0) of std_logic_vector(23 downto 0);
    signal fifol, fifor : fifo_type;


begin -- net-list

    -- Make your net-list here..
    -- The IO-signals and the synchronization are defined in the Altera document..
    read_s <= s_read;
    write_s <= s_write;


    -- Tilstandsregister
    reg:process(CLOCK_50, reset)
    begin
        if(reset = '1') then
            tilstand <= s0;
        elsif (rising_edge(CLOCK_50)) then
            tilstand <= neste;
        end if;
    end process;

    -- Kombinatorikk for registerets nestetilstand og read/write status
    komb:process(tilstand, read_ready, write_ready)
    begin
        s_read <= '0';
        s_write <= '0';
        s_filter <= '0';

        case tilstand is
            when s0 =>                   -- wait
                if (read_ready = '1') then
                    neste <= s1;
                else
                    neste <= s0;
                end if;
            when s1 =>                   -- read
                neste <= s2;
                s_read <= '1';
            when s2 =>                   -- filter
                s_filter <= '1';
                if (write_ready = '1') and (s_filter_ready = '1') then
                    neste <= s3;
                else
                    neste <= s2;
                end if;
            when s3 =>                   -- write
                s_write <= '1';
                neste <= s0;
            when others => neste <= s0;
        end case;

    end process;

    --
    read:process(CLOCK_50)
    begin
        if (rising_edge(CLOCK_50)) then
            if (s_read = '1') then
                --101011110000111100001111
                --111101011110000111100001
                for i in divider - 1 to 23 loop
                    s_read_left(i) <= readdata_left(23);
                    s_read_right(i) <= readdata_right(23);
                end loop;
                s_read_left(23 - divider downto 0) <= readdata_left (23 downto divider);
                s_read_right(23 - divider downto 0) <= readdata_right (23 downto divider);
            end if;
        end if;

    end process;

    filter_pros:process(CLOCK_50)
    begin

        -- endre for beregning
        if (rising_edge(CLOCK_50)) then
            if (s_filter = '1') then
                s_write_left <= s_read_left - fifol(fifo_length - 1) + s_akkl;
                s_write_right <= s_read_right - fifor(fifo_length - 1) + s_akkr;

                for i in 1 to fifo_length - 1 loop
                    fifol(i) <= fifol(i-1);
                    fifor(i) <= fifor(i-1);
                end loop;

                fifol(0) <= s_read_left;
                s_akkl <= s_write_left;
                fifor(0) <= s_read_right;
                s_akkr <= s_write_right;
                s_filter_ready <= '1';
            else
                s_filter_ready <= '0';
            end if;
        end if;
    end process;

    write:process(CLOCK_50)
    begin
        if (rising_edge(CLOCK_50)) then
            if (s_write = '1') then
                writedata_left <= s_write_left;
                writedata_right <= s_write_right;
            end if;
        end if;
    end process;

end architecture;