signal regA, regB, regC, regD : integer range 0 to 3;
   signal regAB, regCD           : integer range 0 to 15;

begin
    process( clk )
    begin
        if( clk'event and clk = '1' ) then
            regA  <= a;
            regB  <= b;
            regC  <= c;
            regD  <= d;
            regAB <= regA * regB;
            regCD <= regC * regD;
            reg   <= regAB * regCD;
        end if;
    end process;