HSEL - SPI Test Code

library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity SPITest1 is
generic(
    DLen: integer := 8;
    Prescaler: integer := 6;
    TestDSize: integer := 8
);

port(
    CS: out std_logic;
    Dat: out std_logic;
    ClkO: out std_logic;
    Bell: out std_logic;
    Clk: in std_logic
);

end entity SPITest1;

architecture ST of SPITest1 is
    signal PresC: unsigned(Prescaler downto 0) := to_unsigned(0, Prescaler+1);
    signal SPS: unsigned(2 downto 0) := "000";
    signal DCnt: unsigned(4 downto 0) := to_unsigned(0, 5);
    signal TestD: unsigned(TestDSize-1 downto 0) := to_unsigned(0, TestDSize);

begin
    process(Clk)
    begin
        if(rising_edge(Clk)) then
        PresC <= PresC+1;
        Bell <= '1';

            if(PresC = 0) then

                if(SPS = "000") then
                    CS <= '0';
                    SPS <= "001";
                elsif(SPS = "001") then
                    ClkO <= '0';
                    Dat <= TestD((DLen-1)-to_integer(DCnt));
                    SPS <= "010";
                elsif(SPS = "010") then
                    ClkO <= '1';
                    DCnt <= DCnt + 1;

                    if(DCnt = DLen) then
                        DCnt <= to_unsigned(0, 5);
                        ClkO <= '0';
                        Dat <= '0';
                        CS <= '1';
                        SPS <= "000";
                        TestD <= TestD + 1;
                    else
                        SPS <= "001";
                    end if;
                end if;
            end if;
        end if;
    end process;
end ST;