library IEEE;
use ieee.std_logic_1164.all;

entity count is
	generic (
			n: integer := 16
		);
		port (
			clear : in std_logic;
			clk : in  std_logic;
			tc : out std_logic;
			q : out std_logic_vector (n-1 downto 0)
		);
end count;

architecture comport of count is
	begin
		process(clk,clear)
			variable valor : std_logic_vector(n-1 downto 0);
			variable co : std_logic_vector(n-1 downto 0);
			variable total : std_logic := '1';
			variable numb: integer := 0;
			begin

				if (clear = '1') then
					for numb in 0 to (n-1) loop
						valor(numb) := '0';
					end loop;
				elsif(rising_edge(clk)) then
					for numb in 0 to (n-1) loop
						if (numb=0) then
							co(numb) := valor(numb) and '1';
							valor(numb) := valor(numb) xor '1';
						else
							co(numb) := valor(numb) and co(numb-1);
							valor(numb) := valor(numb) xor co(numb-1);
						end if;
					end loop;
				end if;

				for numb in 0 to (n-1) loop
					total := total and valor(numb);
				end loop;
				q <= valor;
				tc <= total;
		end process;
end comport;

------------------------------------------------------------------------------------------------

library IEEE;
use ieee.std_logic_1164.all;

entity contador is
	generic (
		gen : integer := 4
	);

	port (
		CLEAR : in std_logic;
		C: in std_logic;
		Q : out std_logic_vector (gen-1 downto 0);
		TC : out std_logic
	);
end contador;

architecture rtl of contador is
	component count is
		generic (
			n: integer := 16
		);
		port (
			clear : in std_logic;
			clk : in  std_logic;
			tc : out std_logic;
			q : out std_logic_vector (n-1 downto 0)
		);
	end component;

begin
r1 : count
	generic map(
		n => gen
	)

	port map (
		clear => CLEAR,
		clk => C,
		q => Q,
		tc => TC
	);
end rtl;