ldr r2,=PMC_BASE
            ldr r0,=TC0_BASE
            ldr r10,=sek
            ldr r11,=min
            ldr r12,=ura
            ldrb r6,[r10]
            ldrb r7,[r11]
            ldrb r8,[r12]

INIT_TC:    STMFD SP!,{r1,LR}

            mov r1,#1 << 17
            str r1,[r2,#PMC_PCER]


            mov r1,#4
            str r1,[r0,#TC_CMR]
            mov r1,#0
            mov r1,#512
            str r1,[r0,#TC_RC]
            mov r1,#5
            str r1,[r0,#TC_CCR]

            bl ls

   ls:      STMFD SP!,{r3-r4,LR}
            ldr r3,[r0,#TC_SR]
            tst r4,#1 << 4
            beq ls
            addne r6,r6,#1
            cmp r6,#59
            movgt r6,#0
            addgt r7,r7,#1
            bls ls
            cmp r7,#59
            movgt r7,#0
            addgt r8,r8,#1
            cmp r8,#24
            movgt r8,#0
            bls ls
            LDMFD SP!,{r3-r4,PC}


sek:  .byte 0
min:  .byte 0
ura:  .byte 0
.equ PMC_BASE, 0xFFFFFC00 /* Power Management Controller */
.equ PMC_PCER, 0x10 /* Peripheral Clock Enable Register */
.equ TC0_BASE, 0xFFFA0000 /* TC0 Channel Base Address */
.equ TC_CCR, 0x00 /* TC0 Channel Control Register */
.equ TC_CMR, 0x04 /* TC0 Channel Mode Register*/
.equ TC_RC, 0x1C /*TC0 Register C */
.equ TC_SR, 0x20 /*TC0 Status Register */