VHDL RS FF

library ieee;
use ieee.std_logic_1164.all;


entity RSFflipFlop is

port(   r,s:    in  std_logic;
    q,qn:   out std_logic);

end RSFflipFlop;



architecture logic of RSFflipFlop is

signal q_cache: std_logic;
signal qn_cache: std_logic;

begin
    q_cache <= r nor qn_cache;
    qn_cache <= s nor q_cache;
    q <= q_cache;
    qn <= qn_cache;
end logic;