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tinymembench on ODROID-C2

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  1. setenv nographics "0"
  2.  
  3. tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
  4.  
  5. ==========================================================================
  6. == Memory bandwidth tests ==
  7. == ==
  8. == Note 1: 1MB = 1000000 bytes ==
  9. == Note 2: Results for 'copy' tests show how many bytes can be ==
  10. == copied per second (adding together read and writen ==
  11. == bytes would have provided twice higher numbers) ==
  12. == Note 3: 2-pass copy means that we are using a small temporary buffer ==
  13. == to first fetch data into it, and only then write it to the ==
  14. == destination (source -> L1 cache, L1 cache -> destination) ==
  15. == Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
  16. == brackets ==
  17. ==========================================================================
  18.  
  19. C copy backwards : 1639.0 MB/s (0.7%)
  20. C copy backwards (32 byte blocks) : 1650.4 MB/s (0.7%)
  21. C copy backwards (64 byte blocks) : 1641.3 MB/s (0.9%)
  22. C copy : 1702.7 MB/s (1.4%)
  23. C copy prefetched (32 bytes step) : 1206.8 MB/s
  24. C copy prefetched (64 bytes step) : 1337.1 MB/s (0.2%)
  25. C 2-pass copy : 1487.0 MB/s (0.2%)
  26. C 2-pass copy prefetched (32 bytes step) : 1034.6 MB/s
  27. C 2-pass copy prefetched (64 bytes step) : 525.1 MB/s
  28. C fill : 3716.5 MB/s
  29. C fill (shuffle within 16 byte blocks) : 3727.8 MB/s (0.4%)
  30. C fill (shuffle within 32 byte blocks) : 3728.3 MB/s
  31. C fill (shuffle within 64 byte blocks) : 3727.9 MB/s
  32. ---
  33. standard memcpy : 1732.1 MB/s
  34. standard memset : 3729.7 MB/s (0.1%)
  35. ---
  36. NEON LDP/STP copy : 1714.5 MB/s
  37. NEON LDP/STP copy pldl2strm (32 bytes step) : 1093.7 MB/s (0.7%)
  38. NEON LDP/STP copy pldl2strm (64 bytes step) : 1367.2 MB/s
  39. NEON LDP/STP copy pldl1keep (32 bytes step) : 2095.4 MB/s
  40. NEON LDP/STP copy pldl1keep (64 bytes step) : 2096.8 MB/s
  41. NEON LD1/ST1 copy : 1724.1 MB/s (0.1%)
  42. NEON STP fill : 3730.1 MB/s (0.1%)
  43. NEON STNP fill : 2495.2 MB/s (0.3%)
  44. ARM LDP/STP copy : 1716.7 MB/s (0.2%)
  45. ARM STP fill : 3729.8 MB/s (0.1%)
  46. ARM STNP fill : 2503.7 MB/s (0.3%)
  47.  
  48. ==========================================================================
  49. == Framebuffer read tests. ==
  50. == ==
  51. == Many ARM devices use a part of the system memory as the framebuffer, ==
  52. == typically mapped as uncached but with write-combining enabled. ==
  53. == Writes to such framebuffers are quite fast, but reads are much ==
  54. == slower and very sensitive to the alignment and the selection of ==
  55. == CPU instructions which are used for accessing memory. ==
  56. == ==
  57. == Many x86 systems allocate the framebuffer in the GPU memory, ==
  58. == accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
  59. == PCI-E is asymmetric and handles reads a lot worse than writes. ==
  60. == ==
  61. == If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
  62. == or preferably >300 MB/s), then using the shadow framebuffer layer ==
  63. == is not necessary in Xorg DDX drivers, resulting in a nice overall ==
  64. == performance improvement. For example, the xf86-video-fbturbo DDX ==
  65. == uses this trick. ==
  66. ==========================================================================
  67.  
  68. NEON LDP/STP copy (from framebuffer) : 209.1 MB/s
  69. NEON LDP/STP 2-pass copy (from framebuffer) : 204.3 MB/s
  70. NEON LD1/ST1 copy (from framebuffer) : 57.1 MB/s
  71. NEON LD1/ST1 2-pass copy (from framebuffer) : 56.6 MB/s
  72. ARM LDP/STP copy (from framebuffer) : 109.7 MB/s
  73. ARM LDP/STP 2-pass copy (from framebuffer) : 108.0 MB/s
  74.  
  75. ==========================================================================
  76. == Memory latency test ==
  77. == ==
  78. == Average time is measured for random memory accesses in the buffers ==
  79. == of different sizes. The larger is the buffer, the more significant ==
  80. == are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
  81. == accesses. For extremely large buffer sizes we are expecting to see ==
  82. == page table walk with several requests to SDRAM for almost every ==
  83. == memory access (though 64MiB is not nearly large enough to experience ==
  84. == this effect to its fullest). ==
  85. == ==
  86. == Note 1: All the numbers are representing extra time, which needs to ==
  87. == be added to L1 cache latency. The cycle timings for L1 cache ==
  88. == latency can be usually found in the processor documentation. ==
  89. == Note 2: Dual random read means that we are simultaneously performing ==
  90. == two independent memory accesses at a time. In the case if ==
  91. == the memory subsystem can't handle multiple outstanding ==
  92. == requests, dual random read has the same timings as two ==
  93. == single reads performed one after another. ==
  94. ==========================================================================
  95.  
  96. block size : single random read / dual random read
  97. 1024 : 0.0 ns / 0.0 ns
  98. 2048 : 0.0 ns / 0.0 ns
  99. 4096 : 0.0 ns / 0.0 ns
  100. 8192 : 0.0 ns / 0.0 ns
  101. 16384 : 0.0 ns / 0.0 ns
  102. 32768 : 0.0 ns / 0.0 ns
  103. 65536 : 4.4 ns / 7.5 ns
  104. 131072 : 6.8 ns / 10.4 ns
  105. 262144 : 8.0 ns / 11.6 ns
  106. 524288 : 10.5 ns / 14.9 ns
  107. 1048576 : 75.4 ns / 114.9 ns
  108. 2097152 : 107.8 ns / 147.3 ns
  109. 4194304 : 130.3 ns / 165.9 ns
  110. 8388608 : 142.0 ns / 174.1 ns
  111. 16777216 : 149.1 ns / 179.9 ns
  112. 33554432 : 153.9 ns / 183.6 ns
  113. 67108864 : 156.8 ns / 186.0 ns
  114.  
  115.  
  116.  
  117. setenv nographics "1"
  118.  
  119. tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
  120.  
  121. ==========================================================================
  122. == Memory bandwidth tests ==
  123. == ==
  124. == Note 1: 1MB = 1000000 bytes ==
  125. == Note 2: Results for 'copy' tests show how many bytes can be ==
  126. == copied per second (adding together read and writen ==
  127. == bytes would have provided twice higher numbers) ==
  128. == Note 3: 2-pass copy means that we are using a small temporary buffer ==
  129. == to first fetch data into it, and only then write it to the ==
  130. == destination (source -> L1 cache, L1 cache -> destination) ==
  131. == Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
  132. == brackets ==
  133. ==========================================================================
  134.  
  135. C copy backwards : 1703.0 MB/s (1.8%)
  136. C copy backwards (32 byte blocks) : 1719.1 MB/s (0.9%)
  137. C copy backwards (64 byte blocks) : 1684.8 MB/s (1.6%)
  138. C copy : 1757.5 MB/s (1.5%)
  139. C copy prefetched (32 bytes step) : 1232.0 MB/s
  140. C copy prefetched (64 bytes step) : 1368.0 MB/s (0.3%)
  141. C 2-pass copy : 1526.5 MB/s
  142. C 2-pass copy prefetched (32 bytes step) : 1057.3 MB/s
  143. C 2-pass copy prefetched (64 bytes step) : 541.0 MB/s (0.3%)
  144. C fill : 3744.1 MB/s (0.2%)
  145. C fill (shuffle within 16 byte blocks) : 3744.0 MB/s
  146. C fill (shuffle within 32 byte blocks) : 3743.8 MB/s
  147. C fill (shuffle within 64 byte blocks) : 3744.0 MB/s
  148. ---
  149. standard memcpy : 1791.0 MB/s (0.3%)
  150. standard memset : 3744.7 MB/s (0.2%)
  151. ---
  152. NEON LDP/STP copy : 1776.6 MB/s (0.3%)
  153. NEON LDP/STP copy pldl2strm (32 bytes step) : 1109.6 MB/s (0.5%)
  154. NEON LDP/STP copy pldl2strm (64 bytes step) : 1398.5 MB/s
  155. NEON LDP/STP copy pldl1keep (32 bytes step) : 2183.0 MB/s
  156. NEON LDP/STP copy pldl1keep (64 bytes step) : 2184.3 MB/s
  157. NEON LD1/ST1 copy : 1784.0 MB/s (0.3%)
  158. NEON STP fill : 3745.0 MB/s (0.2%)
  159. NEON STNP fill : 2781.2 MB/s (0.4%)
  160. ARM LDP/STP copy : 1787.5 MB/s (0.7%)
  161. ARM STP fill : 3745.1 MB/s (0.2%)
  162. ARM STNP fill : 2795.4 MB/s (0.6%)
  163.  
  164. ==========================================================================
  165. == Memory latency test ==
  166. == ==
  167. == Average time is measured for random memory accesses in the buffers ==
  168. == of different sizes. The larger is the buffer, the more significant ==
  169. == are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
  170. == accesses. For extremely large buffer sizes we are expecting to see ==
  171. == page table walk with several requests to SDRAM for almost every ==
  172. == memory access (though 64MiB is not nearly large enough to experience ==
  173. == this effect to its fullest). ==
  174. == ==
  175. == Note 1: All the numbers are representing extra time, which needs to ==
  176. == be added to L1 cache latency. The cycle timings for L1 cache ==
  177. == latency can be usually found in the processor documentation. ==
  178. == Note 2: Dual random read means that we are simultaneously performing ==
  179. == two independent memory accesses at a time. In the case if ==
  180. == the memory subsystem can't handle multiple outstanding ==
  181. == requests, dual random read has the same timings as two ==
  182. == single reads performed one after another. ==
  183. ==========================================================================
  184.  
  185. block size : single random read / dual random read
  186. 1024 : 0.0 ns / 0.0 ns
  187. 2048 : 0.0 ns / 0.0 ns
  188. 4096 : 0.0 ns / 0.0 ns
  189. 8192 : 0.0 ns / 0.0 ns
  190. 16384 : 0.0 ns / 0.0 ns
  191. 32768 : 0.0 ns / 0.0 ns
  192. 65536 : 4.4 ns / 7.5 ns
  193. 131072 : 6.8 ns / 10.4 ns
  194. 262144 : 8.0 ns / 11.6 ns
  195. 524288 : 10.4 ns / 14.8 ns
  196. 1048576 : 73.8 ns / 112.4 ns
  197. 2097152 : 105.4 ns / 144.1 ns
  198. 4194304 : 127.3 ns / 158.0 ns
  199. 8388608 : 138.9 ns / 167.7 ns
  200. 16777216 : 146.2 ns / 173.8 ns
  201. 33554432 : 150.6 ns / 176.8 ns
  202. 67108864 : 153.3 ns / 180.0 ns
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