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-- Company:
-- Engineer:
--
-- Create Date:    11:25:56 03/24/2017
-- Design Name:
-- Module Name:    Keyboard - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Keyboard is
   Port ( PS2_Clk : in STD_LOGIC;
	        Clk_50MHz : in  STD_LOGIC;
           PS2_Data : in  STD_LOGIC
   );
end Keyboard;

architecture Behavioral of Keyboard is

   signal bitCount : integer range 0 to 100 := 0;
   signal scancodeReady : STD_LOGIC := '0';
   signal scancode : STD_LOGIC_VECTOR(7 downto 0);
   signal breakReceived : STD_LOGIC := '0';

   constant keyboardUP : STD_LOGIC_VECTOR(7 downto 0) := "00011101";
   constant keyboardDOWN : STD_LOGIC_VECTOR(7 downto 0) := "00011011";
   constant keyboardRIGHT : STD_LOGIC_VECTOR(7 downto 0) := "00100011";
   constant keyboardLEFT : STD_LOGIC_VECTOR(7 downto 0) := "00011100";
begin

   keyboardCont : process(PS2_Clk)
	begin
		if falling_edge(PS2_Clk) then
			if bitCount = 0 and PS2_Data = '0' then
				scancodeReady <= '0';
				bitCount <= bitCount + 1;
			elsif bitCount > 0 and bitCount < 9 then
				scancode <= PS2_Data & scancode(7 downto 1);
				bitCount <= bitCount + 1;
			elsif bitCount = 9 then
				bitCount <= bitCount + 1;
			elsif bitCount = 10 then
				scancodeReady <= '1';
				bitCount <= 0;
			end if;
		end if;
   end process keyboardCont;



end Behavioral;